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公开(公告)号：US07957923B2
公开(公告)日：2011-06-07
申请号：US12117176
申请日：2008-05-08
CPC分类号： G01R31/31709
摘要： The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal.
摘要翻译： 提供抖动测量装置及其方法。 用于抖动测量的装置包括信号检索模块，信号放大模块，边缘检测模块和时间 - 数字转换模块。 信号检索模块接收待测信号，并检索具有等于被测信号的周期的脉冲宽度的第一脉冲信号。 信号放大模块放大第一脉冲信号的脉冲宽度，从而产生第二脉冲信号。 边缘检测模块检测第二脉冲信号的上升沿和下降沿，并根据各个检测结果生成第一指示信号和第二指示信号。 时间 - 数字转换模块根据第一指示信号和第二指示信号将时域中存在的第二脉冲信号的脉冲宽度转换为数字信号。
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2.发明授权A/D converter and method for converting analog signals into digital signals 有权A / D转换器和将模拟信号转换为数字信号的方法公开(公告)号：US07602324B1
公开(公告)日：2009-10-13
申请号：US12356107
申请日：2009-01-20
申请人： Chih-Haur Huang , Kuo-Chan Huang
发明人： Chih-Haur Huang , Kuo-Chan Huang
IPC分类号： H03M1/20
CPC分类号： H03M1/0641 , H03M1/0695 , H03M1/164 , H03M1/44
摘要： A method for converting analog signals into digital signals includes the steps of: superimposing a dither value on an analog input signal; sampling the superimposition of the analog input signal with the dither value to obtain a sampling signal; converting the sampling signal into corresponding digital values; correcting offsets in the digital values to generate a digital signal; and removing the dither value from the digital signal. An analog-to-digital converter is also disclosed herein.
摘要翻译： 一种将模拟信号转换为数字信号的方法包括以下步骤：将抖动值叠加在模拟输入信号上; 对模拟输入信号与抖动值的叠加进行取样以获得采样信号; 将采样信号转换成相应的数字值; 校正数字值中的偏移量以产生数字信号; 并从数字信号中去除抖动值。 本文还公开了一种模拟 - 数字转换器。
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3.发明申请Source driver output stage circuit, buffer circuit and voltage adjusting method thereof 有权源极驱动器输出级电路，缓冲电路及其电压调整方法公开(公告)号：US20070103208A1
公开(公告)日：2007-05-10
申请号：US11594774
申请日：2006-11-09
申请人： Kuo-Chan Huang , Chih-Haur Huang
发明人： Kuo-Chan Huang , Chih-Haur Huang
IPC分类号： H03B1/00
CPC分类号： H03F3/217 , G09G2310/0275 , G09G2320/0252 , G09G2330/021 , G09G2330/028 , H03F2200/78
摘要： A buffer circuit applied to a source driver output stage circuit includes a buffer and a D-class amplifier. The buffer is coupled to an input voltage for accordingly outputting an output voltage. The D-class amplifier includes a comparator and a switch device. The comparator is for comparing the input voltage and the output voltage and accordingly outputting a comparison signal. The switch device is coupled to an operational voltage for adjusting the output voltage according to the comparison signal.
摘要翻译： 应用于源极驱动器输出级电路的缓冲电路包括缓冲器和D级放大器。 缓冲器耦合到输入电压，从而相应地输出输出电压。 D级放大器包括比较器和开关装置。 比较器用于比较输入电压和输出电压，从而输出比较信号。 开关装置耦合到用于根据比较信号调节输出电压的工作电压。
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4.发明授权Source driver output stage circuit, buffer circuit and voltage adjusting method thereof 有权源极驱动器输出级电路，缓冲电路及其电压调整方法公开(公告)号：US09413310B2
公开(公告)日：2016-08-09
申请号：US11594774
申请日：2006-11-09
申请人： Kuo-Chan Huang , Chih-Haur Huang
发明人： Kuo-Chan Huang , Chih-Haur Huang
IPC分类号： H03F3/217
CPC分类号： H03F3/217 , G09G2310/0275 , G09G2320/0252 , G09G2330/021 , G09G2330/028 , H03F2200/78
摘要： A buffer circuit applied to a source driver output stage circuit includes a buffer and a D-class amplifier. The buffer is coupled to an input voltage for accordingly outputting an output voltage. The D-class amplifier includes a comparator and a switch device. The comparator is for comparing the input voltage and the output voltage and accordingly outputting a comparison signal. The switch device is coupled to an operational voltage for adjusting the output voltage according to the comparison signal.
摘要翻译： 应用于源极驱动器输出级电路的缓冲电路包括缓冲器和D级放大器。 缓冲器耦合到输入电压，从而相应地输出输出电压。 D级放大器包括比较器和开关装置。 比较器用于比较输入电压和输出电压，从而输出比较信号。 开关装置耦合到用于根据比较信号调节输出电压的工作电压。
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公开(公告)号：US20090112499A1
公开(公告)日：2009-04-30
申请号：US12117176
申请日：2008-05-08
IPC分类号： G01R29/26
CPC分类号： G01R31/31709
摘要： The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal.
摘要翻译： 提供抖动测量装置及其方法。 用于抖动测量的装置包括信号检索模块，信号放大模块，边缘检测模块和时间 - 数字转换模块。 信号检索模块接收待测信号，并检索具有等于被测信号的周期的脉冲宽度的第一脉冲信号。 信号放大模块放大第一脉冲信号的脉冲宽度，从而产生第二脉冲信号。 边缘检测模块检测第二脉冲信号的上升沿和下降沿，并根据各个检测结果生成第一指示信号和第二指示信号。 时间 - 数字转换模块根据第一指示信号和第二指示信号将时域中存在的第二脉冲信号的脉冲宽度转换为数字信号。
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公开(公告)号：US08212590B2
公开(公告)日：2012-07-03
申请号：US13067598
申请日：2011-06-13
申请人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
发明人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
IPC分类号： H03B1/00
CPC分类号： H03K19/0013 , H03K3/356113 , H03K19/018521
摘要： A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.
摘要翻译： 混合电压I / O缓冲器包括输入缓冲电路。 输入缓冲电路包括第一反相器，第一电压电平限制电路，第一电压电平上拉电路，输入级电路和逻辑校准电路。 第一反相器反相输入信号以产生第一控制信号。 第一电压电平限制电路限制外部信号的电压电平，以产生传输到第一逆变器的输入信号，以防止第一逆变器的电过载。 第一电压上拉电路由第一控制信号控制，以提高输入到第一反相器的输入信号的电压电平。 输入级电路接收第一控制信号以产生输入到核心电路的相应的数字信号。 当由于输入信号具有低电压电平而使第一反相器误操作时，逻辑校准电路校准第一控制信号的电压电平。
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公开(公告)号：US08165258B2
公开(公告)日：2012-04-24
申请号：US12189204
申请日：2008-08-11
申请人： Meng-Chih Weng , Kuo-Chan Huang
发明人： Meng-Chih Weng , Kuo-Chan Huang
IPC分类号： H03D3/24
摘要： A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node.
摘要翻译： 时钟产生装置包括：分频器，具有耦合到传输接口的输入节点，用于根据从传输接口接收的输入数据产生参考时钟信号; 以及具有耦合到所述传输接口的数据输入节点和耦合到所述分频器的输出节点的参考时钟输入节点的时钟/数据恢复电路，用于根据在所述数据处接收到的所述输入数据之一产生输出时钟信号 输入节点和参考时钟输入节点接收的参考时钟信号。
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公开(公告)号：US20100277216A1
公开(公告)日：2010-11-04
申请号：US12835202
申请日：2010-07-13
申请人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
发明人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , H03K19/018528
摘要： An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.
摘要翻译： 提供输出缓冲电路。 输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。 输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。 电源电压被调整为上拉或下拉输出信号的第一电压电平。
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公开(公告)号：US07786760B2
公开(公告)日：2010-08-31
申请号：US12193299
申请日：2008-08-18
申请人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
发明人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/018528
摘要： An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.
摘要翻译： 提供输出缓冲电路。 输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。 输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。 电源电压被调整为上拉或下拉输出信号的第一电压电平。
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公开(公告)号：US20080252783A1
公开(公告)日：2008-10-16
申请号：US11896216
申请日：2007-08-30
申请人： Tsung-Yi Su , Kuo-Chan Huang
发明人： Tsung-Yi Su , Kuo-Chan Huang
IPC分类号： H04N5/08
摘要： In a device for separating a synchronous signal in a video signal, a capacitor receives the video signal to obtain a coupling signal, a level determining circuit receives the coupling signal and compares a voltage level of the coupling signal with a number of reference voltages. The reference voltages define several reference voltage ranges, one of which is a predetermined reference voltage range. The level determining circuit outputs an adjusting signal according to a reference voltage range corresponding to a minimum voltage level of the coupling signal within a predetermined time period. A level adjusting circuit has several current sources for receiving the adjusting signal and thus controls the current sources to adjust a DC level of the coupling signal. A synchronous signal separating circuit separates the synchronous signal from the coupling signal when the minimum voltage level of the coupling signal is substantially within the predetermined reference voltage range.
摘要翻译： 在用于分离视频信号中的同步信号的装置中，电容器接收视频信号以获得耦合信号，电平确定电路接收耦合信号并将耦合信号的电压电平与多个参考电压进行比较。 参考电压定义了几个参考电压范围，其中一个参考电压范围是预定的参考电压范围。 电平确定电路根据与预定时间段内的耦合信号的最小电压电平相对应的参考电压范围输出调整信号。 电平调整电路具有几个用于接收调节信号的电流源，从而控制电流源来调节耦合信号的直流电平。 当耦合信号的最小电压电平基本上在预定参考电压范围内时，同步信号分离电路将同步信号与耦合信号分离。
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