公开(公告)号：US4933827A

公开(公告)日：1990-06-12

申请号：US376267

申请日：1989-07-06

Applicant: Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

Inventor： Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

IPC: H01L27/04 ,  G11C5/14 ,  G11C16/30 ,  H01L21/822 ,  H02M3/07

CPC classification number: G11C5/145 ,  G11C16/30 ,  H02M3/073

Abstract: The regulation of the output voltage of a voltage multiplier driven by a ring oscillator, an inverter of which is substituted by a NOR gate for providing a terminal through which stopping the oscillation, is effected by controlling the oscillation frequency in function of the current delivered by the voltage multiplier by means of a transistor T1 working as a current generator connected in series with a regulating chain of series-connected diodes by biasing the gate of the transistor with a constant voltage Vref, thus imposing a reference current Iref through the transistor. The voltage signal across the transistor is fed to the input of a first inverter with a preset triggering threshold and the output signal of the inverter is fed through an amplifying and phase-regenerating stage to said terminal for stopping the oscillation of said NOR gate of the ring oscillator. When the discharge current through the regulating chain becomes greater than the imposed current Iref, across the transistor T1 a voltage signal develops which, beyond a certain threshold, determines the switching of the inverter and, through the amplifying and phase-regenerating stage, causes a stop of the oscillation which resumes only when conduction through the regulating chain stops. At steady state the oscillation frequency will result controlled so as to maintain constant the output voltage of the voltage multiplier and to limit the discharge current through the regulating chain thus limiting power consumption.

公开(公告)号：US08856487B2

公开(公告)日：2014-10-07

申请号：US13556066

申请日：2012-07-23

Applicant: Emanuele Confalonieri ,  Corrado Villa

Inventor： Emanuele Confalonieri ,  Corrado Villa

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208

Abstract: Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.

Abstract translation: 用于配置非易失性存储器设备的示例性实施例可以包括将非易失性存储器的M个物理分区配置为两个或更多个存储体，其中两个或多个存储体分别包括M个物理分区中的一个或多个，并且其中至少一个 M个物理分区中的第一个包括第一大小，并且其中至少第二个M个物理分区包括第二大小。

公开(公告)号：US20120290812A1

公开(公告)日：2012-11-15

申请号：US13556066

申请日：2012-07-23

Applicant: Emanuele Confalonieri ,  Corrado Villa

Inventor： Emanuele Confalonieri ,  Corrado Villa

IPC: G06F12/02

CPC classification number: G06F12/00 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208

Abstract: Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.

Abstract translation: 用于配置非易失性存储器设备的示例性实施例可以包括将非易失性存储器的M个物理分区配置为两个或更多个存储体，其中两个或多个存储体分别包括M个物理分区中的一个或多个，并且其中至少一个 M个物理分区中的第一个包括第一大小，并且其中至少第二个M个物理分区包括第二大小。

公开(公告)号：US20100169741A1

公开(公告)日：2010-07-01

申请号：US12623310

申请日：2009-11-20

Applicant: Christophe Laurent ,  Paolo Amato ,  Marco Sforzin ,  Corrado Villa

Inventor： Christophe Laurent ,  Paolo Amato ,  Marco Sforzin ,  Corrado Villa

IPC: H03M13/05 ,  H03M13/09 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/2909

Abstract: A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.

Abstract translation: 公开了一种写入单向非易失性存储单元的存储器阵列和方法，其中用户数据字被转换为内部数据字，并根据小区编码方案写入一个或多个单向数据存储单元。 可以生成对应于内部数据字的检查字。 在一些实施例中，可以通过反转中间检查字的一个或多个位来产生检验字。 可以描述和要求保护其他实施例。

公开(公告)号：US07567107B2

公开(公告)日：2009-07-28

申请号：US11687353

申请日：2007-03-16

Applicant: Daniele Vimercati ,  Stefan Schippers ,  Corrado Villa ,  Yuri Zambelli

Inventor： Daniele Vimercati ,  Stefan Schippers ,  Corrado Villa ,  Yuri Zambelli

IPC: G06F1/04

CPC classification number: H03K5/15013

Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.

Abstract translation: 由输入缓冲器和金属线引入的累积延迟贡献通过使外部信号通过金属线分散而不被缓冲而被分配，所述金属线将缓冲的外部控制信号分配到数据传输电路以执行数据到集成器件和从集成器件传输数据 足够大的尺寸。 这引入了可忽略的本征传播延迟在指定的最大允许输入焊盘电容内。 延迟降低还基于用于每个数据传输电路的本地专用输入缓冲器，并且用于向其施加存在于金属线路上的外部信号的缓冲副本。

公开(公告)号：US20070216449A1

公开(公告)日：2007-09-20

申请号：US11687353

申请日：2007-03-16

Applicant: Daniele Vimercati ,  Stefan Schippers ,  Corrado Villa ,  Yuri Zambelli

Inventor： Daniele Vimercati ,  Stefan Schippers ,  Corrado Villa ,  Yuri Zambelli

IPC: H03B1/00

CPC classification number: H03K5/15013

Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.

Abstract translation: 由输入缓冲器和金属线引入的累积延迟贡献通过使外部信号通过金属线分散而不被缓冲而被分配，所述金属线将缓冲的外部控制信号分配到数据传输电路以执行数据到集成器件和从集成器件传输数据 足够大的尺寸。 这引入了可忽略的本征传播延迟在指定的最大允许输入焊盘电容内。 延迟降低还基于用于每个数据传输电路的本地专用输入缓冲器，并且用于向其施加存在于金属线路上的外部信号的缓冲副本。

公开(公告)号：US20070036014A1

公开(公告)日：2007-02-15

申请号：US11460531

申请日：2006-07-27

Applicant: Efrem Bolandrina ,  Daniele Vimercati ,  Corrado Villa

Inventor： Efrem Bolandrina ,  Daniele Vimercati ,  Corrado Villa

IPC: G11C7/02

CPC classification number: G11C11/5642 ,  G11C16/28 ,  G11C2211/5621 ,  G11C2211/5634

Abstract: A memory device includes a group of memory cells organized in rows and columns and a first addressing circuit for addressing said memory cells of said group on the basis of a cell address. The device further includes a plurality of sets of reference cells, associated to the group, each of said set having a plurality of reference cells, and a second addressing circuit for addressing one of the reference cells during operations of read and verify of addressed memory cells.

Abstract translation: 存储器件包括以行和列组织的一组存储器单元和用于基于单元地址对所述组的所述存储器单元寻址的第一寻址电路。 所述设备还包括与所述组相关联的多组参考单元，所述组中的每一个具有多个参考单元，以及用于在读取和验证寻址的存储器单元的操作期间寻址所述参考单元之一的第二寻址电路 。

公开(公告)号：US20060259847A1

公开(公告)日：2006-11-16

申请号：US11411010

申请日：2006-04-25

Applicant: Corrado Villa

Inventor： Corrado Villa

IPC: H03M13/00

CPC classification number: G06F11/1068

Abstract: An array of non-volatile memory cells includes a row with N cells and M cells. In a partial-storage step, a datum is stored in a first portion of the N cells of the row. A second portion of the N cells of the row are in an “erase” state. A first error correction code associated with the datum is stored in the M cells along with a first enable bit or guard-cell which is indicative of whether the first error correction code is active. The number of M cells, adjacent to the N cells of the row, is defined on the basis of the number N of cells. In the event the datum stored in the first portion of the N cells of the row is subsequently updated or manipulated, a second error correction code associated with the updated or manipulated datum is determined and stored in the second portion of the N cells of the row along with a second enable bit or guard-cell which is indicative of whether the second error correction code is active. At that point, the first enable bit or guard-cell is modified to indicate that the first error correction code is not active.

Abstract translation: 非易失性存储单元的阵列包括具有N个单元和M个单元的行。 在部分存储步骤中，将数据存储在行的N个单元的第一部分中。 该行的N个单元的第二部分处于“擦除”状态。 与数据相关联的第一纠错码与第一使能位或保护单元一起存储在M个单元中，第一使能位或保护单元指示第一纠错码是否有效。 基于单元数N来定义与行的N个单元相邻的M个单元的数量。 在存储在行的N个单元的第一部分中的数据随后被更新或操作的情况下，确定与更新或操纵的数据相关联的第二纠错码并存储在该行的N个单元的第二部分中 以及指示第二纠错码是否有效的第二使能位或保护单元。 此时，修改第一使能位或保护单元以指示第一纠错码未被激活。

公开(公告)号：US20050047226A1

公开(公告)日：2005-03-03

申请号：US10893760

申请日：2004-07-16

Applicant: Andrea Martinelli ,  Daniele Balluchi ,  Corrado Villa

Inventor： Andrea Martinelli ,  Daniele Balluchi ,  Corrado Villa

IPC: G11C7/00 ,  G11C29/00

CPC classification number: G11C29/83

Abstract: A redundancy scheme for a memory integrated circuit having at least two memory sectors and, associated with each memory sector, a respective memory location selector for selecting memory locations within the memory sector according to an address. The redundancy scheme comprises at least one redundant memory sector adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line. A memory sector unusable status indicator element is associated with each memory sector, for controlling the respective power supply control means so as to cause, when set, the selective disconnection of the respective memory location selector from the power supply distribution line.

Abstract translation: 一种用于具有至少两个存储器扇区并且与每个存储器扇区相关联的存储器集成电路的冗余方案，相应的存储器位置选择器用于根据地址选择存储器扇区内的存储器位置。 所述冗余方案包括至少一个适于功能地替代所述至少两个存储器扇区中的一个的冗余存储器扇区，以及冗余控制电路，用于使所述至少一个冗余存储器中的一个被声明为无法使用的存储器扇区的功能替换 部门 冗余控制电路检测对不可用存储器扇区内的存储器位置的访问请求，并将访问请求转发到冗余存储器扇区中的相应冗余存储器位置。 与每个存储器位置选择器相关联，提供相应的电源控制装置，其适于选择性地将相关联的存储器位置选择器连接/断开与电源分配线的连接/断开。 存储器部分不可用状态指示器元件与每个存储器扇区相关联，用于控制相应的电源控制装置，以便在设置时引起各个存储器位置选择器与电源分配线的选择性断开。

公开(公告)号：US5999450A

公开(公告)日：1999-12-07

申请号：US853756

申请日：1997-05-08

Applicant: Marco Dallabora ,  Corrado Villa ,  Marco Defendi

Inventor： Marco Dallabora ,  Corrado Villa ,  Marco Defendi

IPC: G11C16/06 ,  G11C29/02 ,  G11C29/04 ,  G11C29/24 ,  G11C29/44

CPC classification number: G11C29/24 ,  G11C29/02 ,  G11C29/44

Abstract: An electrically erasable and programmable non-volatile memory device comprises at least one memory sector comprising an array of memory cells arranged in rows and first-level columns, the first-level columns being grouped together in groups of first-level columns each coupled to a respective second-level column, first-level selection means for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means for selecting one of the second-level columns, first direct memory access test means activatable in a first test mode for directly coupling a selected memory cell of the array to a respective output terminal of the memory device, redundancy columns of redundancy memory cells for replacing defective columns of memory cells, and a redundancy control circuit comprising defective-address storage means for storing addresses of the defective columns and activating respective redundancy columns when the defective columns are addressed. The redundancy control circuit comprises second direct memory access test means activatable in a second test mode together with the first direct memory access test means for directly coupling memory elements of the defective-address storage means to respective second-level columns of the array, whereby the memory elements of the defective-address storage means can be directly coupled to output terminals of the memory device.

Abstract translation: 电可擦除和可编程的非易失性存储器件包括至少一个存储器扇区，其包括排列成行和第一级列的存储器单元的阵列，所述第一级列按第一级列分组在一起，每一列耦合到 相应的第二级列，用于将每个组的一个第一级列选择性地耦合到相应的第二级列的第一级选择装置，用于选择第二级列之一的第二级选择装置，第一直接存储器访问测试 意味着可以在第一测试模式中激活，用于将阵列的所选择的存储单元直接耦合到存储器件的相应输出端，冗余存储单元的冗余列用于替换存储单元的有缺陷的列，以及冗余控制电路，包括缺陷地址 存储装置，用于存储有缺陷列的地址，并在添加有缺陷列时激活相应的冗余列 退缩 冗余控制电路包括与第一直接存储器存取测试装置一起在第二测试模式下激活的第二直接存储器访问测试装置，用于将缺陷地址存储装置的存储元件直接耦合到阵列的相应第二级列，由此 缺陷地址存储装置的存储元件可以直接耦合到存储器件的输出端。