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公开(公告)号：US08402347B2
公开(公告)日：2013-03-19
申请号：US12623310
申请日：2009-11-20
申请人： Christophe Laurent , Paolo Amato , Marco Sforzin , Corrado Villa
发明人： Christophe Laurent , Paolo Amato , Marco Sforzin , Corrado Villa
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C29/52 , H03M13/2909
摘要： A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.
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公开(公告)号：US20100169741A1
公开(公告)日：2010-07-01
申请号：US12623310
申请日：2009-11-20
申请人： Christophe Laurent , Paolo Amato , Marco Sforzin , Corrado Villa
发明人： Christophe Laurent , Paolo Amato , Marco Sforzin , Corrado Villa
CPC分类号： G06F11/1068 , G11C29/52 , H03M13/2909
摘要： A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.
摘要翻译： 公开了一种写入单向非易失性存储单元的存储器阵列和方法，其中用户数据字被转换为内部数据字，并根据小区编码方案写入一个或多个单向数据存储单元。 可以生成对应于内部数据字的检查字。 在一些实施例中，可以通过反转中间检查字的一个或多个位来产生检验字。 可以描述和要求保护其他实施例。
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公开(公告)号：US20100306446A1
公开(公告)日：2010-12-02
申请号：US12472153
申请日：2009-05-26
摘要： Described herein are methods and devices for controlling power loss. For one embodiment, a method includes issuing a controlled power off command with a controller. The method includes determining whether a memory device is performing a background operation. The method includes safely suspending the background operation or completing the background operation if the memory device is performing the background operation. The method includes safely removing a supply power.
摘要翻译： 这里描述了用于控制功率损耗的方法和装置。 对于一个实施例，一种方法包括用控制器发出受控断电命令。 该方法包括确定存储器件是否正在执行后台操作。 该方法包括：如果存储器件正在执行后台操作，则安全地挂起后台操作或完成后台操作。 该方法包括安全地去除电源。
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4.发明授权Flash EEPROM with controlled discharge time of the word lines and source potentials after erase 失效闪存EEPROM具有受控的字线放电时间和擦除后的源电位
公开(公告)号：US5999456A
公开(公告)日：1999-12-07
申请号：US943391
申请日：1997-10-03
申请人： Mauro Sali , Corrado Villa , Marcello Carrera
发明人： Mauro Sali , Corrado Villa , Marcello Carrera
CPC分类号： G11C16/08
摘要： A Flash EEPROM having at least one memory sector. The memory sector includes a plurality of rows and columns of memory cells; at least one negative voltage generator for generating a negative voltage commonly charging the plurality of rows to a negative potential during an erase pulse for erasing the memory cells of the at least one memory sector and control logic activating the negative voltage generator at the beginning of the erase pulse and deactivating the negative voltage generator at the end of the erase pulse. The Flash EEPROM having for controlling a discharge time of the rows of the at least one memory sector at the end of the erase pulse.
摘要翻译： 具有至少一个存储器扇区的闪存EEPROM。 存储器扇区包括多个存储单元的行和列; 至少一个负电压发生器，用于在用于擦除所述至少一个存储器扇区的存储器单元的擦除脉冲期间产生通常将所述多个行充电至负电位的负电压，以及在所述至少一个存储器扇区的开始处激活所述负电压发生器的控制逻辑 擦除脉冲并在擦除脉冲结束时使负电压发生器去激活。 闪存EEPROM，用于在擦除脉冲结束时控制至少一个存储器扇区的行的放电时间。
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5.发明授权Negative word line voltage regulation circuit for electrically erasable semiconductor memory devices 失效用于电可擦除半导体存储器件的负字线电压调节电路
公开(公告)号：US5920505A
公开(公告)日：1999-07-06
申请号：US881713
申请日：1997-06-23
申请人： Mauro Sali , Corrado Villa , Marcello Carrera
发明人： Mauro Sali , Corrado Villa , Marcello Carrera
CPC分类号： G11C16/30
摘要： A negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device. The circuit regulates a negative word line voltage to be supplied to word lines of the memory device during an electrical erasure of the memory device. The circuit includes an operational amplifier with a first input coupled to a reference voltage, a second input coupled to the negative word line voltage, and an output controlling a voltage regulation branch connected between an external power supply and the negative word line voltage, to provide a regulation current for regulating the negative word line voltage. The output of the operational amplifier also controls a voltage sensing branch, connected between the external power supply and the negative word line voltage, to provide a sensing signal coupled to the second input of the operational amplifier.
摘要翻译： 可在电可擦除半导体存储器件中集成的负字线电压调节电路。 电路在存储器件的电擦除期间调节要提供给存储器件的字线的负字线电压。 电路包括具有耦合到参考电压的第一输入的运算放大器，耦合到负字线电压的第二输入，以及控制连接在外部电源和负字线电压之间的电压调节支路的输出，以提供 用于调节负字线电压的调节电流。 运算放大器的输出还控制连接在外部电源和负字线电压之间的电压感测支路，以提供耦合到运算放大器的第二输入端的感测信号。
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公开(公告)号：US5886949A
公开(公告)日：1999-03-23
申请号：US978665
申请日：1997-11-26
申请人： Corrado Villa , Marco Defendi , Luigi Bettini
发明人： Corrado Villa , Marco Defendi , Luigi Bettini
CPC分类号： G11C8/18
摘要： A method and a circuit generates a pulse synchronization signal in order to control the reading phase of memory cells in semiconductor integrated, electronic memory devices. The pulse synchronization signal is generated upon sensing a change in logic state on at least one of a plurality of address input terminals of the memory cells to also generate an equalization signal for a sense amplifier. The logic state of said pulse synchronization signal is re-acknowledged by a fed-back response having a predetermined delay and being generated upon reception of a corresponding signal to said equalization signal. To this aim, a re-acknowledge circuit portion is provided which is input a corresponding signal to the equalization signal and feedback connected to the output node to drive the discharging of the node with a predetermined delay from the reception of the input signal.
摘要翻译： 方法和电路产生脉冲同步信号，以便控制半导体集成的电子存储器件中存储单元的读取相位。 在感测存储器单元的多个地址输入端中的至少一个上的逻辑状态改变时产生脉冲同步信号，以生成用于读出放大器的均衡信号。 所述脉冲同步信号的逻辑状态由具有预定延迟的反馈响应重新确认，并且在接收到对所述均衡信号的对应信号时产生。 为此目的，提供了一个重新确认电路部分，其输入相应的信号到均衡信号，反馈连接到输出节点，以便从输入信号的接收以预定的延迟驱动节点的放电。
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公开(公告)号：USRE35121E
公开(公告)日：1995-12-12
申请号：US897443
申请日：1992-06-09
申请人： Marco Olivo , Luigi Pascucci , Corrado Villa
发明人： Marco Olivo , Luigi Pascucci , Corrado Villa
摘要： The regulation of the output voltage of a voltage multiplier driven by a ring oscillator, an inverter of which is substituted by a NOR gate for providing a terminal through which stopping the oscillation, is effected by controlling the oscillation frequency in function of the current delivered by the voltage multiplier by means of a transistor T1 working as a current generator connected in series with a regulating chain of series-connected diodes by biasing the gate of the transistor with a constant voltage Vref, thus imposing a reference current Iref through the transistor. The voltage signal across the transistor is fed to the input of a first inverter with a preset triggering threshold and the output signal of the inverter is fed through an amplifying and phase-regenerating stage to said terminal for stopping the oscillation of said NOR gate of the ring oscillator. When the discharge current through the regulating chain becomes greater than the imposed current Iref, across the transistor T1 a voltage signal develops which, beyond a certain threshold, determines the switching of the inverter and, through the amplifying and phase-regenerating stage, causes a stop of the oscillation which resumes only when conduction through the regulating chain stops. At steady state the oscillation frequency will result controlled so as to maintain constant the output voltage of the voltage multiplier and to limit the discharge current through the regulating chain thus limiting power consumption.
摘要翻译： 由环形振荡器驱动的电压倍增器的输出电压的调节通过控制振荡频率来实现，所述环形振荡器的逆变器由NOR门用于提供停止振荡的端子， 通过用作电流发生器的晶体管T1的电压倍增器，其通过以恒定电压Vref偏置晶体管的栅极而与串联二极管的调节链串联连接，从而通过晶体管施加参考电流Iref。 晶体管两端的电压信号以预设的触发阈值馈送到第一反相器的输入端，并且反相器的输出信号通过放大和相位再生级馈送到所述端子，以停止所述NOR门的振荡 环形振荡器。 当通过调节链的放电电流变得大于施加的电流Iref时，跨越晶体管T1产生电压信号，超过一定的阈值，确定逆变器的开关，并且通过放大和相位再生阶段， 仅当通过调节链的导通停止时才恢复振荡的停止。 在稳定状态下，振荡频率将受到控制，以保持电压倍增器的输出电压恒定，并限制放电电流通过调节链，从而限制功耗。
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公开(公告)号：US5258959A
公开(公告)日：1993-11-02
申请号：US810480
申请日：1991-12-19
申请人： Marco Dallabora , Corrado Villa
发明人： Marco Dallabora , Corrado Villa
CPC分类号： G11C16/28
摘要： A memory cell reading circuit has a reference cell bit line and a matrix cell bit line connected to a supply voltage through respective loads and are furthermore connected by normally-off equalization transistors which are enabled by a first clock signal. The bit lines are further connected by normally-off resistive equalization transistors whose resistance is significant in conducting conditions. The equalization transistors are enabled by a first clock signal and the resistive equalization transistors are enabled by a second clock signal which has a duration that extends longer than the first clock signal. The memory cell reading circuit decreases the "read" time required for a memory cell, such as an EPROM cell, as compared to reading circuits previously used.
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公开(公告)号：US4956569A
公开(公告)日：1990-09-11
申请号：US373203
申请日：1989-06-30
申请人： Marco Olivo , Luigi Pascucci , Carlo Riva , Paolo Rosini , Corrado Villa
发明人： Marco Olivo , Luigi Pascucci , Carlo Riva , Paolo Rosini , Corrado Villa
IPC分类号： H01L21/8238 , H01L27/092 , H03K3/356 , H03K3/3565 , H03K19/003
CPC分类号： H03K19/00315 , H03K3/356104 , H03K3/3565
摘要： A CMOS logic circuit for converting a low voltage logic signal with a range O-VCC into a high voltage logic signal with a range O-VPP, which may be entirely made with enhancement-type transistors, comprises an additional p-channel, decoupling transistor functionally connected in series with the p-channel transistor of the CMOS circuit which is connected to the high voltage node VPP and the additional decoupling transistor is driven by a bias voltage tied to the VPP voltage and lower than the latter by a certain preset value. The so-called gated breakdown of p-channel transistors is effectively prevented and furthermore these circuits, destined to operate under a high supply voltage, may be fabricated through a normal CMOS fabrication process not requiring particular fabrication techniques for the p-channel transistors subject to gated breakdown conditions or the formation of depletion-type transistors and without the use of special circuits which require oscillator generated driving signals.
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公开(公告)号：US4922402A
公开(公告)日：1990-05-01
申请号：US372493
申请日：1989-06-28
申请人： Marco Olivo , Luigi Pascucci , Corrado Villa
发明人： Marco Olivo , Luigi Pascucci , Corrado Villa
摘要： A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.
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