公开(公告)号：US20190386096A1

公开(公告)日：2019-12-19

申请号：US16305164

申请日：2017-06-29

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Shinichiro MIYAHARA ,  Atsuya AKIBA ,  Katsumi SUZUKI ,  Yukihiko WATANABE

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/872 ,  H01L29/66

Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.

公开(公告)号：US20190181239A1

公开(公告)日：2019-06-13

申请号：US16278314

申请日：2019-02-18

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Akira AMANO ,  Takayuki SATOMURA ,  Yuichi TAKEUCHI ,  Katsumi SUZUKI ,  Sachiko AOI

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L21/265

Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.

公开(公告)号：US20180151366A1

公开(公告)日：2018-05-31

申请号：US15570841

申请日：2016-04-05

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Takeshi ENDO ,  Atsuya AKIBA ,  Yuichi TAKEUCHI ,  Hidefumi TAKAYA ,  Sachiko AOI

IPC: H01L21/20 ,  H01L29/78 ,  H01L29/16 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L21/2003 ,  H01L21/046 ,  H01L21/265 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/78

Abstract: A semiconductor device includes: a substrate having a cell region with a semiconductor element and an outer peripheral region; and a drift layer on the substrate. The semiconductor element includes a base region, a source region, a trench gate structure, a deep layer deeper than a gate trench, a source electrode, and a drain electrode. The outer peripheral region has a recess portion in which the drift layer are exposed, and a guard ring layer. The guard ring layer includes multiple guard ring trenches having a frame shape, surrounding the cell region and arranged on an exposed surface of the drift layer, and a first guard ring in the guard ring trenches. Each of the linear deep trenches has a width equal to a width of each of the linear guard ring trenches.

公开(公告)号：US20170047394A1

公开(公告)日：2017-02-16

申请号：US15297261

申请日：2016-10-19

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/10 ,  H01L29/808 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/063 ,  H01L21/0455 ,  H01L21/0475 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/8083

Abstract: In a silicon carbide semiconductor device, a trench penetrates a source region and a first gate region and reaches a drift layer. On an inner wall of the trench, a channel layer of a first conductivity-type is formed by epitaxial growth. On the channel layer, a second gate region of a second conductivity-type is formed. A first depressed portion is formed at an end portion of the trench to a position deeper than a thickness of the source region so as to remove the source region at the end portion of the trench. A corner portion of the first depressed portion is covered by a second conductivity-type layer.

Abstract translation: 在碳化硅半导体器件中，沟槽穿透源极区域和第一栅极区域并到达漂移层。 在沟槽的内壁上，通过外延生长形成第一导电类型的沟道层。 在沟道层上形成第二导电类型的第二栅极区域。 第一凹部形成在沟槽的端部至比源极区域的厚度更深的位置，从而去除沟槽端部的源极区域。 第一凹陷部分的角部被第二导电型层覆盖。