公开(公告)号：US20200052112A1

公开(公告)日：2020-02-13

申请号：US16341340

申请日：2017-10-30

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Toru ONISHI ,  Sachiko AOI ,  Yasushi URAKAMI

IPC分类号： H01L29/78 ,  H01L29/423

摘要： In an end portion of a trench, an opening where the end portion of the trench is exposed is formed in a lead-out electrode, a side surface of the trench gate electrode on a top surface side of a semiconductor substrate is spaced from a trench side surface, and a range adjacent to a boundary line positioned between a top surface of the semiconductor substrate and the trench side surface is covered with a laminated insulating film configured such that an interlayer insulating film is laminated on a gate insulating film. This makes it possible to prevent dielectric breakdown of an insulating film.

公开(公告)号：US20180286974A1

公开(公告)日：2018-10-04

申请号：US15765120

申请日：2016-09-16

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Teruaki KUMAZAWA ,  Shinichiro MIYAHARA ,  Sachiko AOI

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/739 ,  H01L23/31 ,  H01L29/10

摘要： A provided method of manufacturing a semiconductor device includes formation of an interlayer insulating. The interlayer insulating film includes first and second insulating layers. The first insulating layer covers an upper surface of each of the gate electrodes. The second insulating layer is located on the first insulating layer. A contact hole is provided in the interlayer insulating film at a position between the trenches. Then the interlayer insulating film is heated at a temperature lower than the softening temperature of the first insulating layer and higher than the softening temperature of the second insulating layer so as to make a surface of the second insulating layer into a curved surface so that surfaces of end portions of the second insulating layer are sloping from the corresponding contact holes so as to be displaced upward toward a center of the corresponding trench.

公开(公告)号：US20180175149A1

公开(公告)日：2018-06-21

申请号：US15576740

申请日：2016-06-03

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Hidefumi TAKAYA ,  Shoji MIZUNO ,  Yukihiko WATANABE ,  Sachiko AOI

IPC分类号： H01L29/16 ,  H01L21/04 ,  H01L21/02 ,  H01L29/423 ,  H01L29/36 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L29/1608 ,  H01L21/02529 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.

公开(公告)号：US20150021680A1

公开(公告)日：2015-01-22

申请号：US14299922

申请日：2014-06-09

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Yukihiko WATANABE ,  Sachiko AOI ,  Hidefumi TAKAYA ,  Atsuya AKIBA

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/7806 ,  H01L21/049 ,  H01L21/0495 ,  H01L27/0255 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/872

摘要： A FET incorporating a Schottky diode has a structure allowing the ratio of an area in which the Schottky diode is formed and an area in which the FET is formed to be freely adjusted. A trench extending for a long distance is utilized. Schottky electrodes are interposed at positions appearing intermittently in the longitudinal direction of the trench. By taking advantage of the growth rate of a thermal oxide film formed on SiC being slower, and the growth rate of a thermal oxide film formed on polysilicon being faster, a structure can be obtained in which insulating film is formed between gate electrodes and Schottky electrodes, between the gate electrodes and a source region, between the gate electrodes and a body region, and between the gate electrodes and a drain region, and in which insulating film is not formed between the Schottky electrodes and the drain region.

摘要翻译： 结合肖特基二极管的FET具有能够自由调节形成肖特基二极管的区域与形成FET的区域的比例的结构。 利用长距离延伸的沟槽。 肖特基电极插入在沟槽的纵向上间断地出现的位置。 通过利用在SiC上形成的热氧化膜的生长速度较慢，并且在多晶硅上形成的热氧化膜的生长速度更快，可以获得在栅电极和肖特基电极之间形成绝缘膜的结构 在栅电极和源极区之间，栅电极与体区之间以及栅电极和漏区之间，并且在肖特基电极和漏极区之间不形成绝缘膜。

公开(公告)号：US20190341308A1

公开(公告)日：2019-11-07

申请号：US16511345

申请日：2019-07-15

申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Yasushi URAKAMI ,  Takehiro KATO ,  Sachiko AOI

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/16

摘要： In a semiconductor device, a semiconductor element is formed in a semiconductor, an interlayer insulating film having a contact hole and containing at least one of phosphorus and boron is disposed above the semiconductor, a metal electrode is disposed above the interlayer insulating film and is connected to the semiconductor element through the contact hole, and the interlayer insulating film is filled with hydrogen.

公开(公告)号：US20190334030A1

公开(公告)日：2019-10-31

申请号：US16505760

申请日：2019-07-09

申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Yuichi TAKEUCHI ,  Atsuya AKIBA ,  Sachiko AOI ,  Katsumi SUZUKI

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/16

摘要： A silicon carbide semiconductor device includes: a vertical semiconductor element, which includes: a semiconductor substrate made of silicon carbide and having a high impurity concentration layer on a back side and a drift layer on a front side; a base region made of silicon carbide on the drift layer; a source region arranged on the base region and made of silicon carbide; a deep layer disposed deeper than the base region; a trench gate structure including a gate insulation film arranged on an inner wall of a gate trench which is arranged deeper than the base region and shallower than the deep layer, and a gate electrode disposed on the gate insulation film; a source electrode electrically connected to the base region, the source region, and the deep layer; and a drain electrode electrically connected to the high impurity concentration layer.

公开(公告)号：US20190058060A1

公开(公告)日：2019-02-21

申请号：US16075840

申请日：2016-12-26

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Jun SAITO ,  Sachiko AOI ,  Yasushi URAKAMI

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/16 ,  H01L29/36 ,  H01L21/04 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/047 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397

摘要： A trench gate semiconductor switching element is provided. The semiconductor substrate of the element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench, and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region. The bottom region includes a first bottom region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench and extending from the bottom surface to a first position; and a second bottom region in contact with the gate insulation layer in a second range adjacent to the first range and extending from the bottom surface to a second position lower than the first position.

公开(公告)号：US20170278923A1

公开(公告)日：2017-09-28

申请号：US15519701

申请日：2015-10-19

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Tatsuji NAGAOKA ,  Hiroki MIYAKE ,  Shinichiro MIYAHARA ,  Sachiko AOI

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L21/761 ,  H01L21/04 ,  H01L29/16 ,  H01L29/872

CPC分类号： H01L29/0623 ,  H01L21/0465 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： A technique stabilizing properties of SBDs is provided. An SBD is provided with a p-type contact region in contact with an anode electrode, and an n-type drift region in Schottky contact with the anode electrode. The p-type contact region includes a first p-type region having a corner portion, a second p-type region connected to the corner portion, and an edge filling portion located at a connection between the first p-type region and the second p-type region. First and second extended lines intersect at an acute angle, where the first extended line is a line extended from a contour of the first p-type region toward the connection and the second extended line is a line extended from a contour of the second p-type region toward the connection. An acute angle edge formed between the first extended line and the second extended line is filled with the edge filling portion.

公开(公告)号：US20160300960A1

公开(公告)日：2016-10-13

申请号：US15092929

申请日：2016-04-07

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Hiroki MIYAKE ,  Tatsuji NAGAOKA ,  Shinichiro MIYAHARA ,  Sachiko AOI

IPC分类号： H01L29/861 ,  H01L21/265 ,  H01L29/66

CPC分类号： H01L21/26513 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： A diode is provided with a semiconductor substrate; an anode electrode located on a front surface of the semiconductor substrate; and a cathode electrode located on a rear surface of the semiconductor substrate. Each of the p-type contact regions includes: a first region being in contact with the anode electrode; a second region located on the rear surface side of the first region, having a p-type impurity density lower than a p-type impurity density in the first region; and a third region located on the rear surface side of the second region and having a p-type impurity density lower than the p-type impurity density in the second region. A thickness of the second region is thicker than a thickness of the first region.

摘要翻译： 二极管设置有半导体衬底; 位于所述半导体衬底的前表面上的阳极; 以及位于半导体衬底的后表面上的阴极电极。 每个p型接触区域包括：与阳极电极接触的第一区域; 位于所述第一区域的背面侧的第二区域，具有比所述第一区域中的p型杂质浓度低的p型杂质浓度; 以及位于第二区域的背面侧的第三区域，并且具有比第二区域中的p型杂质浓度低的p型杂质浓度。 第二区域的厚度比第一区域的厚度厚。

公开(公告)号：US20150084124A1

公开(公告)日：2015-03-26

申请号：US14491332

申请日：2014-09-19

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Jun SAITO ,  Sachiko AOI ,  Yukihiko WATANABE ,  Toshimasa YAMAMOTO

IPC分类号： H01L29/78 ,  H01L29/423

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device includes a semiconductor substrate having an element region and a termination region. The element region includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and first floating regions having the first conductivity type. The termination region includes FLR regions, a second drift region and second floating regions. The FLR regions have the first conductivity type and surrounds the element region. The second drift region has the second conductivity type, makes contact with and surrounds the FLR regions. The second floating regions have the first conductivity type and is surrounded by the second drift region. The second floating regions surround the element region. At least one of the second floating regions is placed at an element region side relative to the closest one of the FLR regions to the element region.

摘要翻译： 半导体器件包括具有元件区域和端接区域的半导体衬底。 元件区域包括具有第一导电类型的第一主体区域，具有第二导电类型的第一漂移区域和具有第一导电类型的第一浮动区域。 终止区域包括FLR区域，第二漂移区域和第二浮动区域。 FLR区域具有第一导电类型并且围绕元件区域。 第二漂移区域具有第二导电类型，与FLR区域接触并围绕FLR区域。 第二浮动区域具有第一导电类型并被第二漂移区域围绕。 第二浮动区域围绕元件区域。 第二浮动区域中的至少一个相对于元件区域中最近的一个FLR区域放置在元件区域侧。