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公开(公告)号:US20190386131A1
公开(公告)日:2019-12-19
申请号:US16304752
申请日:2017-06-29
IPC分类号: H01L29/78 , H01L29/16 , H01L29/06 , H01L29/10 , H01L21/02 , H01L21/04 , H01L21/761 , H01L29/66
摘要: All of intervals between adjacent p type guard rings are set to be equal to or less than an interval between p type deep layers. As a result, the interval between the p type guard rings becomes large, i.e., the trenches are formed sparsely, so that the p type layer is prevented from being formed thick at the guard ring portion when the p type layer is epitaxially grown. Therefore, by removing the p type layer in the cell portion at the time of the etch back process, it is possible to remove the p type layer without leaving any residue in the guard ring portion. Therefore, when forming the p type deep layer, the p type guard ring and the p type connection layer by etching back the p type layer, the residue of the p type layer is restricted from remaining in the guard ring portion.
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公开(公告)号:US20190386096A1
公开(公告)日:2019-12-19
申请号:US16305164
申请日:2017-06-29
IPC分类号: H01L29/06 , H01L29/16 , H01L29/78 , H01L29/872 , H01L29/66
摘要: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.
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公开(公告)号:US20190181239A1
公开(公告)日:2019-06-13
申请号:US16278314
申请日:2019-02-18
发明人: Akira AMANO , Takayuki SATOMURA , Yuichi TAKEUCHI , Katsumi SUZUKI , Sachiko AOI
IPC分类号: H01L29/66 , H01L29/16 , H01L29/78 , H01L21/265
摘要: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.
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公开(公告)号:US20200381313A1
公开(公告)日:2020-12-03
申请号:US16997210
申请日:2020-08-19
发明人: Akira AMANO , Takayuki SATOMURA , Yuichi TAKEUCHI , Katsumi SUZUKI , Sachiko AOI
摘要: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.
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公开(公告)号:US20190214264A1
公开(公告)日:2019-07-11
申请号:US16353670
申请日:2019-03-14
IPC分类号: H01L21/3065 , H01L29/10 , H01L29/66 , H01L29/872 , H01L29/78 , H01L29/16 , H01L23/544 , H01L21/02 , H01L21/311
摘要: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and on which a base layer is formed is prepared, a trench is provided in the base layer, a silicon carbide layer is epitaxially formed on a surface of the base layer while filling the trench with the silicon carbide layer, the sacrificial layer is planarized by reflow after forming the sacrificial layer, and the silicon carbide layer is etched back together with the planarized sacrificial layer by dry etching under an etching condition in which an etching selectivity of the silicon carbide layer to the sacrificial layer is 1.
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公开(公告)号:US20170040441A1
公开(公告)日:2017-02-09
申请号:US15101165
申请日:2014-12-22
发明人: Sachiko AOI , Yukihiko WATANABE , Katsumi SUZUKI , Naohiro SUZUKI
IPC分类号: H01L29/739 , H01L29/06 , H01L29/10 , H01L29/16
CPC分类号: H01L29/7397 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/063 , H01L29/1095 , H01L29/1608 , H01L29/7802 , H01L29/7811 , H01L29/7813
摘要: A resurf layer and a guard ring are formed in a peripheral region in a position at the surface of the semiconductor substrate. The guard ring is formed more deeply than the resurf layer. When the guard ring is shallow and the impurity concentration of the resurf layer is low, the potential distribution at the deep portion of the resurf layer becomes unstable, and the resurf layer does not sufficiently exhibit the effect of improving the withstand voltage. When the guard ring is deep, the impurity concentration of the guard ring is high, the potential distribution at the deep portion of the resurf layer is regulated by the guard ring and the resurf layer sufficiently exhibits the effect of improving the withstand voltage.
摘要翻译: 在半导体基板的表面的位置的周边区域形成有再生层和保护环。 护环形成得比修复层更深。 当保护环较浅并且复合层的杂质浓度低时,再生层深部的电位分布变得不稳定,并且再生层不能充分发挥提高耐电压的效果。 当保护环较深时,保护环的杂质浓度高,再生层深处的电位分布由保护环调节,再生层充分发挥提高耐电压的效果。
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公开(公告)号:US20190386094A1
公开(公告)日:2019-12-19
申请号:US16304783
申请日:2017-06-29
摘要: The width of the p type guard ring is set to match the interval between the adjacent p type guard rings, and the width of the p type guard ring is made larger as the interval between the p type guard rings becomes larger. The width of the frame portion is basically equal to the width of the p type deep layer so that the interval between the frame portions is equal to the interval between the p type deep layers. This makes it possible to reduce the difference in formation areas of the trenches per unit area in the cell portion, the connection portion and the guard ring portion. Therefore, when the p type layer is formed, the difference in the amount of the p type layer embedding into the trenches per unit area also decreases and the thickness of the p type layer is equalized.
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公开(公告)号:US20190334030A1
公开(公告)日:2019-10-31
申请号:US16505760
申请日:2019-07-09
发明人: Yuichi TAKEUCHI , Atsuya AKIBA , Sachiko AOI , Katsumi SUZUKI
IPC分类号: H01L29/78 , H01L29/423 , H01L29/66 , H01L29/16
摘要: A silicon carbide semiconductor device includes: a vertical semiconductor element, which includes: a semiconductor substrate made of silicon carbide and having a high impurity concentration layer on a back side and a drift layer on a front side; a base region made of silicon carbide on the drift layer; a source region arranged on the base region and made of silicon carbide; a deep layer disposed deeper than the base region; a trench gate structure including a gate insulation film arranged on an inner wall of a gate trench which is arranged deeper than the base region and shallower than the deep layer, and a gate electrode disposed on the gate insulation film; a source electrode electrically connected to the base region, the source region, and the deep layer; and a drain electrode electrically connected to the high impurity concentration layer.
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公开(公告)号:US20170012108A1
公开(公告)日:2017-01-12
申请号:US15113475
申请日:2015-01-14
发明人: Jun SAKAKIBARA , Nozomu AKAGI , Shoji MIZUNO , Yuichi TAKEUCHI , Katsumi SUZUKI
CPC分类号: H01L29/66068 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/0262 , H01L21/02634 , H01L21/0465 , H01L21/0475 , H01L21/0485 , H01L21/049 , H01L21/2015 , H01L21/2033 , H01L21/266 , H01L21/3065 , H01L21/3083 , H01L23/544 , H01L29/0615 , H01L29/0619 , H01L29/0865 , H01L29/0882 , H01L29/0886 , H01L29/1037 , H01L29/1045 , H01L29/105 , H01L29/1095 , H01L29/1608 , H01L29/401 , H01L29/41741 , H01L29/41766 , H01L29/66484 , H01L29/66666 , H01L29/66734 , H01L29/7396 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/7831 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要: In a method for manufacturing a semiconductor device, when a second conductive type impurity layer is formed to provide a deep layer having a second conductive type in a first concavity and to provide a channel layer having the second conductive type on a surface of a drift layer, an epitaxial growth is performed under a growth condition that a contact trench provided by a recess is formed on a surface of a part of the second conductive type impurity layer corresponding to a center position of the first concavity, and a contact region is formed by ion-implanting a second conductive type impurity on a bottom of the contact trench.
摘要翻译: 在制造半导体器件的方法中,当形成第二导电型杂质层以在第一凹部中提供具有第二导电类型的深层并且在漂移层的表面上提供具有第二导电类型的沟道层 在与第一凹部的中心位置对应的第二导电型杂质层的一部分的表面上形成由凹部设置的接触沟槽的生长条件进行外延生长,并且接触区域由 在接触沟槽的底部离子注入第二导电型杂质。
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公开(公告)号:US20190386095A1
公开(公告)日:2019-12-19
申请号:US16304866
申请日:2017-06-29
摘要: Intervals of the frame portion and the p type guard ring on a cell portion side are made narrower than other parts, and the narrowed part provides a dot line portion. By narrowing the intervals of the frame portion and the p type guard ring on the cell portion side, the electric field concentration is reduced on the cell portion side, and the equipotential line directs to more outer circumferential side. By providing the dot line portions, the difference in the formation areas of the trench per unit area in the cell portion, the connection portion and the guard ring portion is reduced, and the thicknesses of the p type layers formed on the cell portion, the connection portion and the guard ring portion are uniformed. Thereby, when etching-back the p type layer, the p type layer is prevented from remaining as a residue in the guard ring portion.
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