公开(公告)号：US06514805B2

公开(公告)日：2003-02-04

申请号：US09896532

申请日：2001-06-30

Applicant: Daniel Xu ,  Erman Bengu ,  Ming Jin

Inventor： Daniel Xu ,  Erman Bengu ,  Ming Jin

IPC: H01L2100

CPC classification number: H01L21/76229 ,  H01L21/76232 ,  H01L27/24

Abstract: A method comprising forming a first trench in a substrate, and forming a second trench in the substrate, the second trench intersecting the first trench and having a retrograde sidewall profile relative to a direction from a top of the trench to a bottom of the trench. An apparatus comprising a matrix of cells in a substrate formed by a plurality of first trenches and a plurality of second trenches, the plurality of second trenches intersecting the plurality of first trenches and having a retrograde sidewall profile relative to a direction from a top to a bottom of the respective trench; and an electrically accessible storage device coupled to respective ones of the matrix of cells.

Abstract translation: 一种方法，包括在衬底中形成第一沟槽，以及在所述衬底中形成第二沟槽，所述第二沟槽与所述第一沟槽相交并且具有相对于从所述沟槽的顶部到所述沟槽的底部的方向的逆向侧壁轮廓。 一种包括由多个第一沟槽和多个第二沟槽形成的衬底中的单元阵列的装置，所述多个第二沟槽与所述多个第一沟槽相交并且具有相对于从顶部到顶部的方向的逆向侧壁轮廓 相应沟槽的底部; 以及耦合到所述单元阵列中的相应单元的电可存储存储设备。

公开(公告)号：US06462984B1

公开(公告)日：2002-10-08

申请号：US09895599

申请日：2001-06-29

Applicant: Daniel Xu ,  Tyler A. Lowrey ,  David L. Kencke

Inventor： Daniel Xu ,  Tyler A. Lowrey ,  David L. Kencke

IPC: G11C1136

CPC classification number: G11C13/003 ,  G11C8/08 ,  G11C11/36 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

Abstract: An integrated circuit (IC) has a number of memory cells, each of which has a diode structure coupled between a bitline and a wordline that are selected when programming that cell. A target memory cell of the IC is programmed while simultaneously floating a number of unselected bitlines and wordlines in the IC.

Abstract translation: 集成电路（IC）具有多个存储单元，每个存储单元具有耦合在编程该单元时选择的位线和字线之间的二极管结构。 IC的目标存储单元被编程，同时浮置IC中的多个未选定的位线和字线。

公开(公告)号：US06437383B1

公开(公告)日：2002-08-20

申请号：US09745322

申请日：2000-12-21

Applicant: Daniel Xu

Inventor： Daniel Xu

IPC: H01L2972

CPC classification number: H01L21/76229 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: The invention relates to a phase-change memory device. The device includes a double-trench isolation structure around the diode stack that communicates to the lower electrode. The present invention also relates to a method of making a phase-change memory device. The method includes forming two orthogonal and intersecting isolation trenches around a memory cell structure diode stack.

Abstract translation: 本发明涉及一种相变存储器件。 该器件包括二极管堆叠周围的双沟槽隔离结构，其与下部电极连通。 本发明还涉及一种制造相变存储器件的方法。 该方法包括在存储单元结构二极管堆叠周围形成两个正交和相交的隔离沟槽。