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    Low cost multi-state magnetic memory
    34.
    发明授权
    Low cost multi-state magnetic memory 有权
    低成本多状态磁存储器

    公开(公告)号：US08330240B2

    公开(公告)日：2012-12-11

    申请号：US13213026

    申请日：2011-08-18

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: H01L29/82 ,  G11C11/00

    CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607

    Abstract: A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer.

    Abstract translation: 多状态电流切换磁存储元件具有磁隧道结（MTJ），用于存储多于一位的信息。 MTJ包括固定层，阻挡层和不均匀的自由层。 在一个实施例中，当每个单元具有2位时，当四个不同电平的电流之一被施加到存储元件时，所施加的电流使MTJ的非均匀自由层切换到四个不同的磁状态之一。 MTJ的宽开关电流分布是非均匀自由层的宽晶粒尺寸分布的结果。

    Non-volatile magnetic memory with low switching current and high thermal stability
    35.
    发明授权
    Non-volatile magnetic memory with low switching current and high thermal stability 有权
    具有低开关电流和高热稳定性的非易失性磁存储器

    公开(公告)号：US08310020B2

    公开(公告)日：2012-11-13

    申请号：US13455888

    申请日：2012-04-25

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod

    IPC: H01L29/82 ,  G11C11/00

    CPC classification number: H01L43/10 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228

    Abstract: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer and a top electrode formed on top of the cap layer.

    Abstract translation: 非易失性电流切换磁存储元件包括底电极，形成在底电极顶部的钉扎层和形成在钉扎层顶部上的固定层。 存储元件还包括形成在钉扎层顶部的隧道层，形成在隧道层顶部上的第一自由层，形成在自由层顶部上的颗粒膜层，形成在颗粒状的顶部上的第二自由层 膜层，形成在第二层的顶部上的盖层和形成在盖层的顶部上的顶部电极。

    Non-Volatile Perpendicular Magnetic Memory with Low Switching Current and High Thermal Stability
    36.
    发明申请
    Non-Volatile Perpendicular Magnetic Memory with Low Switching Current and High Thermal Stability 有权
    具有低开关电流和高热稳定性的非易失性垂直磁存储器

    公开(公告)号：US20120212998A1

    公开(公告)日：2012-08-23

    申请号：US13453940

    申请日：2012-04-23

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod

    IPC: G11C11/16 ,  H01L43/10

    CPC classification number: H01L43/10 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228

    Abstract: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The non-volatile current-switching magnetic memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer with a perpendicular anisotropy that is formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer, and a top electrode formed on top of the cap layer.

    Abstract translation: 非易失性电流切换磁存储元件包括底电极，形成在底电极顶部的钉扎层和形成在钉扎层顶部上的固定层。 非易失性电流切换磁存储元件还包括形成在钉扎层顶部的隧道层，形成在隧道层顶部上的具有垂直各向异性的第一自由层，形成在隧道层顶部的粒状膜层 自由层，形成在所述粒状膜层的顶部上的第二自由层，形成在所述第二层的顶部上的盖层，以及形成在所述盖层的顶部上的顶部电极。

    Internal CMOS reference generator and voltage regulator
    37.
    发明授权
    Internal CMOS reference generator and voltage regulator 失效
    内部CMOS参考发生器和稳压器

    公开(公告)号：US6018265A

    公开(公告)日：2000-01-25

    申请号：US52038

    申请日：1998-03-30

    Applicant: Parviz Keshtbod

    Inventor： Parviz Keshtbod

    IPC: G11C16/06 ,  G05F1/10 ,  G05F3/02 ,  G05F3/24

    CPC classification number: G05F3/247

    Abstract: The present invention includes a circuit for deriving a reference signal having a reference voltage from a system voltage source having a system voltage level and for regulating the reference voltage level. The circuit includes an output sub-circuit, a reference generator sub-circuit, a regulator sub-circuit, a translator sub-circuit, and a low pass filter sub-circuit. The output sub-circuit, which is coupled to the system voltage source, is responsive to a voltage control signal, and is operative to generate the reference signal wherein the reference voltage level is less than or equal to the system voltage level. The reference generator sub-circuit is responsive to the reference signal and is operative to generate a prime voltage level which remains substantially unaffected by fabrication process variations, temperature variations and variations in the reference signal. The regulator sub-circuit is responsive to the reference signal and the prime voltage level and is operative to generate the voltage control signal. The translator sub-circuit is coupled to the system voltage source and functions to amplify the voltage control signal. The low pass filter sub-circuit is used for filtering the voltage control signal. The output sub-circuit includes an output transistor having its gate coupled to receive the voltage control signal, its source connected to the system voltage source, and its drain connected to an output terminal at which the reference signal is provided.

    Abstract translation: 本发明包括用于从具有系统电压电平的系统电压源导出具有参考电压并用于调节参考电压电平的参考信号的电路。 电路包括输出子电路，参考发生器子电路，调节器子电路，转换器子电路和低通滤波器子电路。 耦合到系统电压源的输出子电路响应于电压控制信号，并且可操作地产生参考信号，其中参考电压电平小于或等于系统电压电平。 参考发生器子电路响应于参考信号，并且可操作地产生主要电压电平，其基本上不受制造工艺变化，温度变化和参考信号变化的影响。 稳压器子电路响应于参考信号和主电压电平，并且可操作地产生电压控制信号。 转换器子电路耦合到系统电压源并且用于放大电压控制信号。 低通滤波器子电路用于对电压控制信号进行滤波。 输出子电路包括输出晶体管，其输出晶体管的栅极被耦合以接收电压控制信号，其源极连接到系统电压源，其漏极连接到提供参考信号的输出端子。

    Spacer flash cell process
    38.
    发明授权
    Spacer flash cell process 失效
    间隔闪存单元过程

    公开(公告)号：US5776787A

    公开(公告)日：1998-07-07

    申请号：US650785

    申请日：1996-05-20

    Applicant: Parviz Keshtbod

    Inventor： Parviz Keshtbod

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a metal, preferably tungsten or a tungsten alloy. The field oxide is selectively removed. A gate oxide is grown and a first polysilicon layer is formed and then etched to form spacers along the edges of the metal/second insulator structure. The first polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A second polysilicon layer is formed over the tunneling insulator.

    Abstract translation: 闪存EPROM单元在编程期间通过在浮动栅极和位线之间提供垂直耦合而具有减小的单元尺寸。 擦除操作是通过将电子从Poly间隔物的尖端引导到控制栅极进行的。 单元被适配成使得阵列内的每个单元的源极是相邻单元的源极，漏极是另一相邻单元的漏极。 通过在优选为场氧化物的第一绝缘体中的开口将漏区形成为衬底而形成电池。 第二绝缘体沉积在第一绝缘体上方，在衬底上并且沿着开口的侧壁，并且优选地是薄层，使得开口被薄绝缘层覆盖。 绝缘开口填充有金属，优选钨或钨合金。 有选择地去除场氧化物。 生长栅极氧化物并形成第一多晶硅层，然后蚀刻以沿着金属/第二绝缘体结构的边缘形成间隔物。 选择性地蚀刻第一多晶硅，并在其上形成隧穿绝缘体层。 在隧道绝缘体上形成第二多晶硅层。

    Spacer flash cell process
    39.
    发明授权
    Spacer flash cell process 失效
    间隔闪存单元过程

    公开(公告)号：US5476801A

    公开(公告)日：1995-12-19

    申请号：US383090

    申请日：1995-02-03

    Applicant: Parviz Keshtbod

    Inventor： Parviz Keshtbod

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/441

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer. The field oxide is selectively removed. A gate oxide is grown and a second polysilicon layer is formed and then etched to form spacers along the edges of the first polysilicon/second insulator structure. The second polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A third polysilicon layer is formed over the tunneling insulator.

    Abstract translation: 闪存EPROM单元在编程期间通过在浮动栅极和位线之间提供垂直耦合而具有减小的单元尺寸。 擦除操作是通过将电子从Poly间隔物的尖端引导到控制栅极进行的。 单元被适配成使得阵列内的每个单元的源极是相邻单元的源极，漏极是另一相邻单元的漏极。 通过在优选为场氧化物的第一绝缘体中的开口将漏区形成为衬底而形成电池。 第二绝缘体沉积在第一绝缘体上方，在衬底上并且沿着开口的侧壁，并且优选地是薄层，使得开口被薄绝缘层覆盖。 绝缘开口填充有第一掺杂多晶硅层。 有选择地去除场氧化物。 生长栅极氧化物并形成第二多晶硅层，然后蚀刻以沿着第一多晶硅/第二绝缘体结构的边缘形成间隔物。 选择性地蚀刻第二多晶硅，并在其上形成隧穿绝缘体层。 在隧道绝缘体上形成第三多晶硅层。

    Method for manufacturing high density non-volatile magnetic memory
    40.
    发明授权
    Method for manufacturing high density non-volatile magnetic memory 有权
    高密度非挥发性磁记忆体的制造方法

    公开(公告)号：US08802451B2

    公开(公告)日：2014-08-12

    申请号：US13610587

    申请日：2012-09-11

    Applicant: Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

    Inventor： Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

    IPC: H01L21/00

    CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/161 ,  H01L27/228

    Abstract: Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.

    Abstract translation: 描述使用两个正交线图案化步骤制造MTJ阵列的方法。 描述了使用用于一个或两个正交线图案化步骤的自对准双图案化方法来实现特征尺寸为最小光刻特征尺寸（F）的一半的MTJ的致密阵列的实施例。 在一组实施例中，选择提供掩模功能的层叠层的材料和厚度，使得在初始掩模焊盘组被图案化之后，一系列蚀刻步骤逐渐地将掩模焊盘形状传递通过多个掩模 通过所有的MTJ单元层的层和下层形成完整的MTJ柱。 在另一组实施例中，在沉积顶部电极层之前，将MTJ / BE叠层图案化成平行线。

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