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31.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A DOUBLE BLOCKED SUM OF ABSOLUTE DIFFERENCES 有权用于执行双重阻塞的绝对差异的系统，装置和方法公开(公告)号：US20140019713A1
公开(公告)日：2014-01-16
申请号：US13992229
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F15/78
CPC分类号： G06F9/3001 , G06F7/50 , G06F7/544 , G06F9/30036 , G06F9/3836 , G06F9/3877 , G06F15/78 , G06F2207/5442
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.
摘要翻译： 用于在计算机处理器中执行的系统，装置和方法的实施例响应于包括目的地向量寄存器操作数的绝对差指令的单向量双块压缩和，绝对差（SAD）的双块压缩和，第一和第二 描述源操作数，立即数和操作码。
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32.发明申请PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO GENERATE SEQUENCES OF INTEGERS IN NUMERICAL ORDER THAT DIFFER BY A CONSTANT STRIDE 审中-公开处理器，方法，系统和指令，用于生成恒定序列的数字序列中的整数序列公开(公告)号：US20130283019A1
公开(公告)日：2013-10-24
申请号：US13977349
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four non-negative integers in numerical order with all integers in consecutive positions differing by a constant stride of at least two. In an aspect, storing the result including the sequence of the at least four integers is performed without calculating the at least four integers using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一方面的方法包括接收指示目的地存储位置的指令。 结果存储在目的地存储位置以响应该指令。 结果包括以数字顺序的至少四个非负整数的序列，其中连续位置中的所有整数与至少两个的恒定步幅相差。 在一方面，使用前一条指令的结果，在不计算至少四个整数的情况下执行存储包括至少四个整数的序列的结果。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US20140006755A1
公开(公告)日：2014-01-02
申请号：US13538523
申请日：2012-06-29
申请人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
发明人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F7/52 , G06F9/30018 , G06F9/30036
摘要： An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
摘要翻译： 描述了具有指令执行流水线的装置，其具有支持向量乘法加法指令的向量功能单元。 向量乘以相乘指令乘以两个向量的各个K位元素，并将其各自产物的一部分与X位累加器中的另一个相应输入操作数进行累加，其中X大于K.
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34.发明申请PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO GENERATE SEQUENCES OF CONSECUTIVE INTEGERS IN NUMERICAL ORDER 审中-公开处理器，方法，系统和指令，用于生成数字序列中的数字整数序列公开(公告)号：US20130275482A1
公开(公告)日：2013-10-17
申请号：US13976766
申请日：2011-12-22
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four consecutive non-negative integers in numerical order. In an aspect, the instruction does not indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一方面的方法包括接收指示目的地存储位置的指令。 结果存储在目的地存储位置以响应该指令。 结果包括数字顺序的至少四个连续的非负整数的序列。 在一方面，该指令不表示在架构可见的存储位置中具有多个打包数据元素的源打包数据操作数。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US10095516B2
公开(公告)日：2018-10-09
申请号：US13538523
申请日：2012-06-29
申请人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
发明人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
摘要： An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
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36.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A HORIZONTAL ADD OR SUBTRACT IN RESPONSE TO A SINGLE INSTRUCTION 有权用于执行水平添加或分类的系统，设备和方法对单一指令的响应公开(公告)号：US20140013075A1
公开(公告)日：2014-01-09
申请号：US13992230
申请日：2011-12-23
申请人： Mostafa Hagog , Elmoustapha Ould-Aumed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Mostafa Hagog , Elmoustapha Ould-Aumed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30167 , G06F9/30185 , G06F15/8053 , G06F2207/5442
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, and an opcode are describes.
摘要翻译： 用于在计算机处理器中执行的系统，装置和方法的实施例响应于包括目的地向量寄存器操作数，源向量寄存器操作数，单向量封装的水平加法或减法指令，对打包数据元素进行水平加或减， 并描述操作码。
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公开(公告)号：US09092226B2
公开(公告)日：2015-07-28
申请号：US13325559
申请日：2011-12-14
申请人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Amit Gradstein , Guy Bale , Thierry Pons
发明人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Amit Gradstein , Guy Bale , Thierry Pons
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： Methods and apparatus are provided for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one example a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one example a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
摘要翻译： 提供了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。 在一个示例中，识别用于SIMD浮点运算的数字异常，并且启动SIMD微操作以生成用于SIMD浮点运算的打包结果的两个打包部分结果。 启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。 标志被设置和存储与打包部分结果以识别异常元素。 在一个示例中，当SIMD归一化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。
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公开(公告)号：US20140188967A1
公开(公告)日：2014-07-03
申请号：US13729421
申请日：2012-12-28
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F17/10
摘要： In one embodiment, a processor includes at least one floating point unit. The at least one floating point unit may include an adder, leading change anticipator (LCA) logic, and a shifter. The adder may be to add a first operand X and a second operand Y to obtain an output operand having a bit length n. The LCA logic may be to: for each bit position i from n−1 to 1, obtain a set of propagation values and a set of bit values based on the first operand X and the second operand Y; and generate a LCA mask based on the set of propagation values and the set of bit values. The shifter may be to normalize the output operand based on the LCA mask. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括至少一个浮点单元。 所述至少一个浮点单元可以包括加法器，引导改变预测器（LCA）逻辑和移位器。 加法器可以添加第一操作数X和第二操作数Y以获得具有位长度n的输出操作数。 LCA逻辑可以是：对于从n-1到1的每个比特位置i，基于第一操作数X和第二操作数Y获得一组传播值和一组比特值; 并且基于传播值集合和位值集合来生成LCA掩码。 移位器可以是基于LCA掩码来规范化输出操作数。 描述和要求保护其他实施例。
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公开(公告)号：US20120166509A1
公开(公告)日：2012-06-28
申请号：US12976359
申请日：2010-12-22
IPC分类号： G06F7/38
CPC分类号： G06F7/535 , G06F7/5525 , G06F9/30014 , G06F2207/5356 , G06F2207/5521
摘要： In one embodiment, the present invention includes a method for receiving a reciprocal instruction and an operand in a processor, accessing an entry of a lookup table based on a portion of the operand and the instruction, generating an encoder output based on a type of the reciprocal instruction and whether the reciprocal instruction is a legacy instruction, and selecting portions of the lookup table entry and input operand to be provided to a reciprocal logic unit based on the encoder output. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于在处理器中接收互逆指令和操作数的方法，其基于所述操作数和所述指令的一部分访问查找表的条目，基于所述操作数的类型生成编码器输出 互逆指令以及互易指令是否是遗留指令，以及基于编码器输出来选择要提供给倒数逻辑单元的查找表项和输入操作数的部分。 描述和要求保护其他实施例。
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公开(公告)号：US20140379773A1
公开(公告)日：2014-12-25
申请号：US13926175
申请日：2013-06-25
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
CPC分类号： G06F7/483 , G06F7/5443 , G06F7/764
摘要： Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
摘要翻译： 提供了执行融合乘法（FMA）操作的系统和方法。 在一个实施例中，由FMA操作使用的加法器的长度小于3 * N，其中N是浮点数的尾数项中的位数。 可以使用掩码来使用加法器来执行FMA操作的相加部分。 如果发生下溢，则可以使用第二掩模来对FMA操作的添加部分的结果进行非规范化。
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