公开(公告)号：US5937325A

公开(公告)日：1999-08-10

申请号：US966306

申请日：1997-11-07

Applicant: Emi Ishida

Inventor： Emi Ishida

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/268

CPC classification number: H01L29/665 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/4941 ,  H01L29/66507

Abstract: A method of forming a titanium silicide (69) includes the steps of forming a transistor having a source region (58), a drain region (60) and a gate structure (56) and forming a titanium layer (66) over the transistor. A first anneal is performed with a laser anneal at an energy level that causes the titanium layer (66) to react with the gate structure (56) to form a high resistivity titanium silicide phase (68) having substantially small grain sizes. The unreacted portions of the titanium layer (66) are removed and a second anneal is performed, thereby causing the high resistivity titanium silicide phase (68) to convert to a low resistivity titanium silicide phase (69). The small grain sizes obtained by the first anneal allow low resistivity titanium silicide phase (69) to be achieved at device geometries less than about 0.25 micron.

Abstract translation: 形成硅化钛（69）的方法包括以下步骤：形成具有源极区（58），漏极区（60）和栅极结构（56）并在晶体管上形成钛层（66）的晶体管。 以能量水平进行激光退火来执行第一退火，该能级导致钛层（66）与栅极结构（56）反应以形成具有基本上小的晶粒尺寸的高电阻率硅化钛相（68）。 除去钛层（66）的未反应部分，进行第二退火，从而使高电阻率钛硅化物相（68）转化为低电阻率硅化钛相（69）。 通过第一退火获得的小晶粒尺寸允许在小于约0.25微米的器件几何形状下实现低电阻率硅化钛相（69）。

公开(公告)号：US06455385B1

公开(公告)日：2002-09-24

申请号：US09003751

申请日：1998-01-07

Applicant: Roger L. Alvis ,  Emi Ishida

Inventor： Roger L. Alvis ,  Emi Ishida

IPC: H01L21265

CPC classification number: H01L29/78 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/324

Abstract: A method of reducing implant dose loss is provided. The method includes performing multiple low dose implant steps with interspersed anneal steps, thereby avoiding amorphous-silicon formation. The anneal steps may be performed at high temperatures or at low temperatures.

Abstract translation: 提供减少植入剂量损失的方法。 该方法包括执行具有散置退火步骤的多个低剂量注入步骤，从而避免非晶硅形成。 退火步骤可以在高温或低温下进行。

公开(公告)号：US06423601B1

公开(公告)日：2002-07-23

申请号：US09667685

申请日：2000-11-14

Applicant: Emi Ishida ,  Ming Yin Hao

Inventor： Emi Ishida ,  Ming Yin Hao

IPC: H01L21336

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/823814 ,  H01L29/6659

Abstract: Submicron-dimensioned, p-channel MOS transistors and CMOS devices a formed using nitrogen and boron co-implants for forming p-type well regions, each implant having a parabolically-shaped concentration distribution profile. During subsequent thermal annealling, boron-doped wells are formed, each having a retrograde-shaped concentration distribution profile exhibiting a peak boron concentration at a preselected depth below the semiconductor substrate surface. The inventive method reduces “short-channel” effects such as “punch-through” while maintaining high channel mobility.

Abstract translation: 使用用于形成p型阱区的氮和硼共注入物形成的亚微米尺寸的p沟道MOS晶体管和CMOS器件a，每个植入物具有抛物线形的浓度分布曲线。 在随后的热退火期间，形成硼掺杂的阱，每个具有在半导体衬底表面下方的预选深度处呈现峰值硼浓度的逆向浓度分布分布。 本发明的方法在保持高信道移动性的同时减少了“短通道”效应，例如“穿透”。

公开(公告)号：US06410393B1

公开(公告)日：2002-06-25

申请号：US09639797

申请日：2000-08-17

Applicant: Ming-Yin Hao ,  Emi Ishida

Inventor： Ming-Yin Hao ,  Emi Ishida

IPC: H01L21336

CPC classification number: H01L29/66659 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/7835

Abstract: Short channel effects are curtailed thereby increasing integrated circuit speed by forming a channel dopant with an asymmetric impurity concentration profile. Embodiments include ion implanting Si or Ge at a large tilt angle to amorphize a portion of a designated channel region with a varying degree of amorphization decreasing from the intended drain region to the intended source region, substantially vertically ion implanting channel dopant impurities and annealing. During annealing, diffusion is retarded in areas of increased amorphization, thereby forming an asymmetric impurity concentration gradient across the channel region increasing in the direction of the source region.

Abstract translation: 缩短通道效应，从而通过形成具有不对称杂质浓度分布的沟道掺杂剂来提高集成电路速度。 实施例包括以大的倾斜角度离子注入Si或Ge，以使指定通道区域的一部分非晶化，其中不同程度的非晶化从预期的漏极区域到预期的源极区域，基本上垂直离子注入沟道掺杂剂杂质和退火。 在退火过程中，在非晶化过程增大的区域中扩散被延迟，从而在源极区域的方向上跨越沟道区域形成不对称杂质浓度梯度。

公开(公告)号：US06337260B1

公开(公告)日：2002-01-08

申请号：US09667602

申请日：2000-09-22

Applicant: Emi Ishida

Inventor： Emi Ishida

IPC: H01L21322

CPC classification number: H01L21/31155 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26526

Abstract: Transient enhanced diffusion (TED) of ion implanted dopant impurities within a silicon semiconductor substrate is eliminated or substantially reduced by displacing “knocked-on” oxygen atoms from an overlying oxygen-containing layer into the substrate by ion implantation. The “knocked-on” oxygen atoms getter silicon interstitial atoms generated within the substrate by dopant implantation, which are responsible for TED.

Abstract translation: 通过离子注入将“敲入”的氧原子从上覆的含氧层置换到衬底中，消除或基本上减少硅半导体衬底内离子注入的掺杂杂质的瞬态增强扩散（TED）。 “敲入”氧原子通过掺杂剂注入在衬底内产生的硅间隙原子，这是负责TED的。

公开(公告)号：US06190980B1

公开(公告)日：2001-02-20

申请号：US09150874

申请日：1998-09-10

Applicant: Bin Yu ,  Ming-Ren Lin ,  Emi Ishida

Inventor： Bin Yu ,  Ming-Ren Lin ,  Emi Ishida

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/26586 ,  H01L29/66492 ,  H01L29/66537

Abstract: A method of performing tilted implantation for pocket, halo and source/drain extensions in ULSI dense structures. The method overcomes the process limit, due to shadowing effects, in dense structures, of using large angle tilted implant techniques in ULSI circuits. A gate opening in an oxide layer is defined and partially filled by insertion of nitride spacers to define an actual gate window opening. The small angle tilted implant technique has the equivalent doping effect of large angle tilted implants, and circumvents the maximum angle limit (&thgr;MAX) that occurs in the large angle implant method. The small angle tilted implant technique also automatically provides self alignment of the pocket/halo/extension implant to the gate of the device.

Abstract translation: 在ULSI致密结构中进行凹槽，晕圈和源极/漏极延伸的倾斜注入的方法。 该方法克服了在密集结构中的阴影效应，在ULSI电路中使用大角度倾斜植入技术的过程极限。 通过插入氮化物间隔物限定氧化层中的开口，并且通过插入氮化物间隔物来部分地填充以限定实际的门窗开口。 小角度倾斜植入技术具有大角度倾斜植入物的等效掺杂效应，并避开了大角度植入法中发生的最大角度限制（thetaMAX）。 小角度倾斜植入技术还自动提供袋/晕/延伸植入物到装置的门的自对准。

公开(公告)号：US6100171A

公开(公告)日：2000-08-08

申请号：US33784

申请日：1998-03-03

Applicant: Emi Ishida

Inventor： Emi Ishida

IPC: H01L21/268 ,  H01L21/28 ,  H01L21/336 ,  H01L21/42

CPC classification number: H01L29/6659 ,  H01L21/268 ,  H01L21/28035

Abstract: In one embodiment, the present invention relates to a method of removing fluorine from a gate conductor involving the steps of providing a semiconductor device containing a substrate, a gate insulator layer overlying a portion of the substrate, a gate conductor containing fluorine overlying the gate insulator layer, and a source and a drain region adjacent the gate insulator layer; and laser annealing the semiconductor device at an energy level sufficient to melt at least a portion of the gate conductor thereby inducing the removal of fluorine from the gate conductor. In another embodiment, the present invention relates to a method of making a transistor involving the steps of forming a gate conductor overlying a gate insulator layer, wherein the gate conductor and the gate insulator layer overlie a portion of a substrate, doping the substrate and gate conductor with BF.sub.2.sup.+ to form in the substrate a source region and a drain region adjacent the gate insulator layer and a channel region between the source and drain regions and under the gate insulator layer; laser annealing the doped gate conductor, the doped source region and the doped drain region at an energy level sufficient to melt at least a portion of the doped gate conductor, thereby removing fluorine from the melted portion of the gate conductor; and subsequently performing an RTA to activate the doped source region and the doped drain region

Abstract translation: 在一个实施例中，本发明涉及一种从栅极导体去除氟的方法，包括以下步骤：提供包含衬底的半导体器件，覆盖衬底的一部分的栅极绝缘体层， 以及与栅极绝缘体层相邻的源极和漏极区域; 以及以足以熔化所述栅极导体的至少一部分的能级激光退火所述半导体器件，从而导致从所述栅极导体去除氟。 在另一个实施例中，本发明涉及一种制造晶体管的方法，该方法包括以下步骤：形成覆盖栅极绝缘体层的栅极导体，其中栅极导体和栅极绝缘体层覆盖在衬底的一部分上，掺杂衬底和栅极 导体与BF2 +在衬底中形成与栅极绝缘体层相邻的源极区域和漏极区域以及源极和漏极区域之间的沟道区域以及栅极绝缘体层下方的沟道区域; 激光退火所述掺杂栅极导体，所述掺杂源极区域和所述掺杂漏极区域处于足以熔化所述掺杂栅极导体的至少一部分的能级，从而从所述栅极导体的熔融部分去除氟; 随后执行RTA以激活掺杂源极区域和掺杂漏极区域

公开(公告)号：US6074937A

公开(公告)日：2000-06-13

申请号：US58897

申请日：1998-04-13

Applicant: Shekhar Pramanick ,  Che-Hoo Ng ,  Emi Ishida

Inventor： Shekhar Pramanick ,  Che-Hoo Ng ,  Emi Ishida

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/425

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/2652

Abstract: Lightly doped regions are implanted into an amorphous region in the semiconductor substrate to significantly reduce transient enhanced diffusion upon subsequent activation annealing. A sub-surface non-amorphous region is also formed before activation annealing to substantially eliminate end-of-range defects on crystallization of amorphous region containing the lightly doped implants.

Abstract translation: 将轻掺杂区域注入到半导体衬底中的非晶区域中，以在随后的激活退火时显着减少瞬时增强的扩散。 在激活退火之前还形成亚表面非非晶区域，以基本上消除含有轻掺杂植入物的非晶区域的结晶范围内的范围内缺陷。

公开(公告)号：US5966605A

公开(公告)日：1999-10-12

申请号：US966308

申请日：1997-11-07

Applicant: Emi Ishida

Inventor： Emi Ishida

IPC: H01L21/223 ,  H01L21/225 ,  H01L21/268 ,  H01L21/28 ,  H01L21/336

CPC classification number: H01L29/66575 ,  H01L21/28035 ,  H01L21/223 ,  H01L21/2254 ,  H01L21/268

Abstract: A method of forming a transistor includes the steps of forming a gate structure (56) overlying a gate oxide layer (54), wherein the gate structure (56) and gate oxide layer (54) overlie a substrate (50), thereby separating the substrate (50) into a first region (90) and a second region (92) with a channel region therebetween. The method also includes doping the gate structure (56), the first region (90) and the second region (92) and annealing the doped gate structure (56) with a laser anneal, thereby driving the dopant through a substantial depth of the gate structure (56). Lastly, a source region (94) and a drain region (96) are formed in the first region (90) and the second region (92), respectively, wherein the dopant is further driven into the gate structure (56). Consequently, the dopant is driven substantially deeper in the gate structure (56) than in the shallow source region (94) and drain region (96) junctions to allow decoupling of poly depletion from the need for shallow junctions.

Abstract translation: 一种形成晶体管的方法包括以下步骤：形成覆盖栅极氧化物层（54）的栅极结构（56），其中栅极结构（56）和栅极氧化物层（54）覆盖在衬底（50）上， 衬底（50）插入到其间具有沟道区域的第一区域（90）和第二区域（92）中。 该方法还包括掺杂栅极结构（56），第一区域（90）和第二区域（92）并且用激光退火退火掺杂栅极结构（56），从而驱动掺杂剂通过栅极的大的深度 结构（56）。 最后，分别在第一区域（90）和第二区域（92）中形成源极区（94）和漏极区（96），其中掺杂剂进一步被驱动到栅极结构（56）中。 因此，掺杂剂在栅极结构（56）中比在浅源极区（94）和漏极区（96）中接合地被驱动得更深，以允许多余的去耦从需要浅结的位置。

公开(公告)号：US5795627A

公开(公告)日：1998-08-18

申请号：US799236

申请日：1997-02-14

Applicant: Sunil Mehta ,  Emi Ishida ,  Xiao-Yu Li

Inventor： Sunil Mehta ,  Emi Ishida ,  Xiao-Yu Li

IPC: H01L21/316 ,  H01L21/762 ,  H01L27/115 ,  C23C14/04

CPC classification number: H01L21/76213 ,  H01L21/316 ,  H01L27/115

Abstract: A method of forming an oxide enhancing region, such as phosphorus, in a semiconductor substrate with minimal damage is provided. The method includes the steps of forming an oxide enhancing region in the semiconductor substrate to a depth below the semiconductor substrate. A 308 nm excimer laser is then applied to the oxide enhancing region in order to reduce the damage caused by forming the oxide enhancing region. A uniform and reliable oxide layer is then formed on the surface of the substrate over the damage reduced oxide enhancing region.

Abstract translation: 提供了在具有最小损伤的半导体衬底中形成诸如磷的氧化物增强区域的方法。 该方法包括以下步骤：在半导体衬底中形成半导体衬底下方的深度的氧化物增强区。 然后将308nm准分子激光器施加到氧化物增强区域，以便减少由形成氧化物增强区域引起的损伤。 然后在损伤还原氧化物增强区域上的衬底的表面上形成均匀且可靠的氧化物层。