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45 条记录 (耗时 0.031 秒)

    Lithium ion secondary battery
    34.
    发明授权
    Lithium ion secondary battery 失效
    锂离子二次电池

    公开(公告)号：US06727021B1

    公开(公告)日：2004-04-27

    申请号：US09581244

    申请日：2000-06-26

    申请人： Hisashi Shiota ,  Hiroaki Urushibata ,  Tetsuo Mitani ,  Fusaoki Uchikawa

    发明人： Hisashi Shiota ,  Hiroaki Urushibata ,  Tetsuo Mitani ,  Fusaoki Uchikawa

    IPC分类号： H01M462

    CPC分类号： H01M4/66 ,  H01M4/02 ,  H01M4/13 ,  H01M4/62 ,  H01M4/624 ,  H01M10/0525 ,  H01M10/0583 ,  H01M10/0587

    摘要： A multilayer electrode battery which restrains temperature rise produced by an internal short circuit and has a compact size and a large battery capacity. The battery is a multilayer electrode battery which uses an electrode formed by providing positive temperature coefficient characteristics to at least one of an active material and an electronic conductive material in contact with the active material, and a collector of at least one of a positive electrode and a negative electrode, and which has a plurality of layers of multilayer electrode bodies.

    摘要翻译： 一种抑制由内部短路产生的温度上升并且具有紧凑的尺寸和大的电池容量的多层电极电池。 电池是使用通过向与活性物质接触的活性物质和电子导电材料中的至少一种提供正温度系数特性而形成的电极的多层电极电池，以及正极和 负极，并且具有多层多层电极体。

    Compound superconducting wire and method for manufacturing the same
    36.
    发明授权
    Compound superconducting wire and method for manufacturing the same 失效
    复合超导线及其制造方法

    公开(公告)号：US5753862A

    公开(公告)日：1998-05-19

    申请号：US167061

    申请日：1993-12-16

    申请人： Yoshio Kubo ,  Kunihiko Egawa ,  Hiroko Higuma ,  Takayuki Nagai ,  Fusaoki Uchikawa

    发明人： Yoshio Kubo ,  Kunihiko Egawa ,  Hiroko Higuma ,  Takayuki Nagai ,  Fusaoki Uchikawa

    IPC分类号： C22F1/00 ,  H01B12/10 ,  H01B13/00 ,  H01L39/24 ,  H01B12/00

    CPC分类号： H01L39/2403 ,  H01L39/2409 ,  Y10S505/812 ,  Y10S505/821 ,  Y10S505/884 ,  Y10T29/49014 ,  Y10T428/12438 ,  Y10T428/12486

    摘要： A compound superconducting wire comprising a matrix of CuX alloy and a multiplicity of Z.sub.3 X filaments embedded in the matrix in a spaced relationship so as not to come into contact with each other wherein X is Sn or Ga and Z.sub.3 X is Nb.sub.3 Sn or V.sub.3 Ga. In a precursor, therefore, a multiplicity of filaments of a base metal material Z such as Nb are arranged in a Cu base metal metrix concentrically in layers around a center core of a base metal material X such as Sn, in which the spacing between any adjacent filaments arranged in a former boundary region of an .epsilon.-phase bronze layer having a certain radius from the center produced when the precursor is preheat-treated at a temperature of 300.degree. to 600.degree. C. is made larger than the spacing between any adjacent filaments arranged in the other matrix regions. Also disclosed is a precursor wire wherein a composite of a Cu base metal material and a base metal material X capable of forming an alloy with the Cu base metal material is used as a matrix without arranging a core of the base metal material X at the center, and a multiplicity of filaments of a base metal material Z are embedded in the composite in a spaced relationship.

    摘要翻译： 一种复合超导线，其包含CuX合金基体和以相互间隔的关系嵌入基体中的多个Z3X细丝，以便彼此不接触，其中X是Sn或Ga，Z3X是Nb3Sn或V3Ga。 因此，在前体中，诸如Nb之类的贱金属材料Z的多根细丝围绕着诸如Sn之类的基体金属材料X（例如Sn）的中心芯以同心的方式排列在铜基金属晶体中， 布置在从300度到600度的温度下进行预热处理时产生的中心产生的具有一定半径的ε相青铜层的前边界区域中的相邻长丝的尺寸大于任何相邻 布置在其他矩阵区域中的细丝。 还公开了一种母体线，其中使用能够与Cu基底金属材料形成合金的Cu基底金属材料和贱金属材料X的复合物作为基体，而不将基体金属材料X的芯排列在中心 ，并且多个基体金属材料Z的长丝以间隔的关系嵌入复合材料中。

    Process for producing a temperature and moisture sensitive element
    37.
    发明授权
    Process for producing a temperature and moisture sensitive element 失效
    生产温湿度敏感元件的方法

    公开(公告)号：US4731257A

    公开(公告)日：1988-03-15

    申请号：US800024

    申请日：1985-11-20

    申请人： Fusaoki Uchikawa

    发明人： Fusaoki Uchikawa

    IPC分类号： G01K7/22 ,  G01N27/12 ,  B05D5/12

    CPC分类号： G01N27/121 ,  G01K7/223

    摘要： A process for producing a temperature and moisture sensitive element, which comprises a step of forming a first coating layer by applying a composition comprising a polymerized organo-silicon compound and an inorganic material onto a substrate, a step of forming a second coating layer apart from the first coating layer by applying the same composition as defined above onto the substrate, a step of heat-treating the first coating layer to form a moisture sensitive section, and a step of treating the second coating layer to form a temperature sensitive section by a treatment different from the heat treatment of the first coating layer.

    摘要翻译： 一种用于生产温度和湿度敏感元件的方法，其包括通过将包含聚合的有机硅化合物和无机材料的组合物施加到基材上形成第一涂层的步骤，形成第二涂层的步骤 通过将与上述相同的组成施加到基材上的第一涂层，对第一涂层进行热处理以形成湿敏部分的步骤，以及通过以下步骤处理第二涂层以形成温度敏感部分的步骤： 处理与第一涂层的热处理不同。

    Film bulk acoustic wave device
    40.
    发明授权
    Film bulk acoustic wave device 失效
    薄膜体声波装置

    公开(公告)号：US06586861B2

    公开(公告)日：2003-07-01

    申请号：US09892606

    申请日：2001-06-28

    申请人： Koichiro Misu ,  Kenji Yoshida ,  Koji Ibata ,  Shusou Wadaka ,  Tsutomu Nagatsuka ,  Fusaoki Uchikawa ,  Akira Yamada ,  Chisako Maeda

    发明人： Koichiro Misu ,  Kenji Yoshida ,  Koji Ibata ,  Shusou Wadaka ,  Tsutomu Nagatsuka ,  Fusaoki Uchikawa ,  Akira Yamada ,  Chisako Maeda

    IPC分类号： H01L41047

    CPC分类号： H03H9/174 ,  H03H3/04 ,  H03H9/02133 ,  H03H9/02157 ,  H03H9/176 ,  H03H2003/0428

    摘要： There is provided a film bulk acoustic wave device comprising: a silicon substrate 1, a dielectric film 21 including a silicon nitride 16 formed on the substrate 1 and a silicon oxide 2 on the silicon nitride 16, a bottom electrode 3 formed on the dielectric film 21, a piezoelectric film 17 formed on the bottom electrode 3, and a top electrode 5 formed on the piezoelectric film 17, wherein a via hole is formed in such a manner that the thickness direction of a part of the silicon substrate 1 which is opposite to a region including a part where the top electrode 5 exists is removed from the bottom surface of the silicon substrate 1 to a boundary surface with the silicon nitride 16.

    摘要翻译： 本发明提供一种薄膜压电元件，其特征在于，具备硅基板1，在基板1上形成有氮化硅16的电介质膜21和在氮化硅16上形成的氧化硅2，在电介质膜上形成的底部电极3 如图21所示，形成在底部电极3上的压电膜17和形成在压电膜17上的顶部电极5，其中形成通孔，使得硅衬底1的与其相对的部分的厚度方向 到包括顶部电极5存在的部分的区域从硅衬底1的底表面去除到与氮化硅16的边界面的区域。