公开(公告)号：US20190267946A1

公开(公告)日：2019-08-29

申请号：US16367113

申请日：2019-03-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafiullah Syed ,  Abdellatif Bellaouar ,  Chi Zhang

IPC: H03F1/02 ,  H03F3/195 ,  H04B1/04 ,  H03F3/217

Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.

公开(公告)号：US10326420B1

公开(公告)日：2019-06-18

申请号：US15966998

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Abdellatif Bellaouar ,  Mehmet Ipek ,  Frank Zhang

IPC: H03F3/45 ,  H03F3/193 ,  H03F3/21 ,  H04B1/16

Abstract: We disclose a receiver circuit which may be used in mm-wave devices. The receiver circuit comprises a transimpedance amplifier comprising PMOS and NMOS transistors, wherein the back gate voltages provided to the transistors may be adjusted. By adjusting the back gate voltages during device operation, structural variations and temperature variations in the threshold voltages of the transistors may be minimized and the gain compression tolerance of the receiver circuit may be increased.

公开(公告)号：US09774302B1

公开(公告)日：2017-09-26

申请号：US15277344

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Abdellatif Bellaouar ,  Sher Jiun Fang

IPC: H03F1/34 ,  H03F3/195

CPC classification number: H03F1/342 ,  H03F3/193 ,  H03F3/195 ,  H03F3/265 ,  H03F3/45179 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/555 ,  H03F2200/72 ,  H03F2200/75

Abstract: Disclosed is an amplifier circuit having a single-ended input and differential outputs. The differential outputs are achieved using a first output branch and a second output branch, each including a common source FET (CS-FET) and a common gate FET (CG-FET) connected in series between ground and a corresponding out node connected to a load. An input signal is applied to the CS-FET in the first output branch and an intermediate signal at an intermediate node between the CS-FET and the CG-FET in the first output branch is applied to the CS-FET in the second output branch. The CG-FET in the first output branch and the CS-FET in the second output branch are equal in size such that their transconductances are approximately equal, such that currents in the two output branches are inverted and the outputs at the output nodes of the two output branches are differential outputs.