公开(公告)号：US10348243B2

公开(公告)日：2019-07-09

申请号：US15213529

申请日：2016-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chi Zhang ,  Arul Balasubramaniyan

IPC: G05F1/10 ,  H03B5/12 ,  H03J5/00

Abstract: Embodiments of the present disclosure provide a circuit structure including: a switching transistor including a gate terminal, a back-gate terminal, a source terminal, and a drain terminal; a biasing node coupled to the back-gate terminal of the switching transistor, the biasing node being alternately selectable between an on state and an off state; a first capacitor source-coupled to the switching transistor; a second capacitor drain-coupled to the switching capacitor; and a first enabling node source-coupled to the switching transistor, the first enabling node being alternately selectable between an on state and an off state.

公开(公告)号：US10332960B2

公开(公告)日：2019-06-25

申请号：US15370004

申请日：2016-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chi Zhang

IPC: H03B5/12 ,  H01L27/08 ,  H01L27/12 ,  H01L29/06 ,  H01L29/76 ,  H01L29/93 ,  H01L29/94

Abstract: A digitally controlled varactor device comprising: a set of bulk nMOS field effect transistors bulk tied to a ground, the set bulk nMOS field effect transistors having: a first transistor including: a source coupled to a DC voltage source; and a gate coupled to a digitally controlled oscillator; a second transistor including: a source coupled to the DC voltage source; and a gate coupled to the digitally controlled oscillator; and a third transistor including: a source coupled to a drain of the first transistor; and a drain coupled to a drain of the second transistor. The transistors in the digitally controlled varactor may be FDSOI nMOS devices with backgate coupled to a DC voltage source.

公开(公告)号：US10680557B2

公开(公告)日：2020-06-09

申请号：US16367113

申请日：2019-03-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafiullah Syed ,  Abdellatif Bellaouar ,  Chi Zhang

IPC: H03F1/02 ,  H03F3/195 ,  H04B1/04 ,  H03F3/45 ,  H03F3/217 ,  H03F1/14 ,  H01L21/84 ,  H01L27/12

Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.

公开(公告)号：US20190267946A1

公开(公告)日：2019-08-29

申请号：US16367113

申请日：2019-03-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafiullah Syed ,  Abdellatif Bellaouar ,  Chi Zhang

IPC: H03F1/02 ,  H03F3/195 ,  H04B1/04 ,  H03F3/217

Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.

公开(公告)号：US10291183B1

公开(公告)日：2019-05-14

申请号：US15908678

申请日：2018-02-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafiullah Syed ,  Abdellatif Bellaouar ,  Chi Zhang

IPC: H03F1/02 ,  H03F3/195 ,  H03F3/21 ,  H03F3/45 ,  H03F1/22 ,  H04B1/04 ,  H03F3/217 ,  H01L21/84 ,  H01L27/12

Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.

公开(公告)号：US20180026580A1

公开(公告)日：2018-01-25

申请号：US15213529

申请日：2016-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chi Zhang ,  Arul Balasubramaniyan

IPC: H03B5/12

CPC classification number: H03B5/1265 ,  H03B5/1212 ,  H03B5/1228 ,  H03B2200/004 ,  H03J5/00

Abstract: Embodiments of the present disclosure provide a circuit structure including: a switching transistor including a gate terminal, a back-gate terminal, a source terminal, and a drain terminal; a biasing node coupled to the back-gate terminal of the switching transistor, the biasing node being alternately selectable between an on state and an off state; a first capacitor source-coupled to the switching transistor; a second capacitor drain-coupled to the switching capacitor; and a first enabling node source-coupled to the switching transistor, the first enabling node being alternately selectable between an on state and an off state.

公开(公告)号：US10574245B2

公开(公告)日：2020-02-25

申请号：US15979263

申请日：2018-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chi Zhang

IPC: H03L7/099 ,  H01L27/06 ,  H03B5/12 ,  H03L7/093

Abstract: A digitally controlled oscillator (DCO) may include a transformer, which may contain a secondary winding comprising a first port, a second port, and an array of capacitor units, wherein each capacitor unit includes a first NFET having a gate and a back gate connected to a control signal, and a drain connected to the first port; a second NFET having a gate connected to ground, a back gate connected to the control signal, and a drain connected to the source of the first NFET; and a third NFET having a gate and a back gate connected to the control signal, a drain connected to the source of the second NFET, and a source connected to the second port. The capacitor units may allow fine tuning of the DCO output frequency with a resolution of about 0.3 MHz and a range of about 80 MHz.

公开(公告)号：US20190296751A1

公开(公告)日：2019-09-26

申请号：US15979263

申请日：2018-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chi Zhang

IPC: H03L7/099 ,  H01L27/06 ,  H03L7/093 ,  H03B5/12

Abstract: A digitally controlled oscillator (DCO) may include a transformer, which may contain a secondary winding comprising a first port, a second port, and an array of capacitor units, wherein each capacitor unit includes a first NFET having a gate and a back gate connected to a control signal, and a drain connected to the first port; a second NFET having a gate connected to ground, a back gate connected to the control signal, and a drain connected to the source of the first NFET; and a third NFET having a gate and a back gate connected to the control signal, a drain connected to the source of the second NFET, and a source connected to the second port. The capacitor units may allow fine tuning of the DCO output frequency with a resolution of about 0.3 MHz and a range of about 80 MHz.

公开(公告)号：US20180159471A1

公开(公告)日：2018-06-07

申请号：US15370004

申请日：2016-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chi Zhang

IPC: H03B5/12 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L27/0811 ,  H01L27/1203 ,  H01L29/76 ,  H01L29/78 ,  H01L29/93 ,  H01L29/94 ,  H03B5/12 ,  H03B5/1206 ,  H03B5/1253 ,  H03B2201/0208 ,  H03B2201/0266

Abstract: A digitally controlled varactor device comprising: a set of bulk nMOS field effect transistors bulk tied to a ground, the set bulk nMOS field effect transistors having: a first transistor including: a source coupled to a DC voltage source; and a gate coupled to a digitally controlled oscillator; a second transistor including: a source coupled to the DC voltage source; and a gate coupled to the digitally controlled oscillator; and a third transistor including: a source coupled to a drain of the first transistor; and a drain coupled to a drain of the second transistor. The transistors in the digitally controlled varactor may be FDSOI nMOS devices with backgate coupled to a DC voltage source.