公开(公告)号：US20190229019A1

公开(公告)日：2019-07-25

申请号：US15878081

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Xusheng Wu ,  Haigou Huang ,  John H. Zhang ,  Pei Liu ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.

公开(公告)号：US10276391B1

公开(公告)日：2019-04-30

申请号：US16007127

申请日：2018-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417

Abstract: Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate structure includes a work function metal layer, a first conductor layer, and a second conductor layer arranged over the work function metal layer. The second conductor layer has a sidewall and a top surface, and the first conductor layer has a first section arranged between the second conductor layer and the work function metal layer and a second section arranged adjacent to a first portion of the sidewall of the second conductor layer. A dielectric cap is arranged on the gate structure. The dielectric cap has a first section arranged over the top surface of the second conductor layer and a second section arranged adjacent to a second portion of the sidewall of the second conductor layer.

公开(公告)号：US20150111373A1

公开(公告)日：2015-04-23

申请号：US14057357

申请日：2013-10-18

Applicant: GLOBALFOUNDRIES, INC. ,  International Business Machines Corporation

Inventor： William J. Cote ,  Laertis Economikos ,  Shom Ponoth ,  Theodorus E. Standaert ,  Charan V. Surisetty ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823828 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823864

Abstract: A method of forming transistors is provided. The method includes forming a plurality of transistor structures to have a plurality of dummy gates on a substrate. Each dummy gate is surrounded by sidewall spacers of a height, which is less than the dummy gate and is different for different transistor structures resulting in divots of different depths above the sidewall spacers. The method then deposits a conformal dielectric layer on top of the dummy gates and inside the divots of the plurality of transistor structures with the conformal dielectric layer having a thickness of at least half of a width of the divots, removes only a portion of the conformal dielectric layer that is on top of the dummy gates to expose the dummy gates; and replaces the dummy gates with a plurality of high-k metal gates.

Abstract translation: 提供一种形成晶体管的方法。 该方法包括形成多个晶体管结构以在衬底上具有多个虚拟栅极。 每个虚拟栅极被高度的侧壁间隔物包围，该间隙小于虚拟栅极，并且对于不同的晶体管结构是不同的，导致在侧壁间隔物上方具有不同深度的裂缝。 该方法然后在保持电介质层的厚度至少为纹理宽度的一半之上的情况下，在虚拟栅极的顶部和多个晶体管结构的纹间之内沉积保形介电层，仅去除一部分保形 位于伪栅极顶部以暴露伪栅极的介电层; 并且用多个高k金属栅极代替伪栅极。

公开(公告)号：US10741451B2

公开(公告)日：2020-08-11

申请号：US16150651

申请日：2018-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Shesh Mani Pandey ,  Chanro Park ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.

公开(公告)号：US20200185509A1

公开(公告)日：2020-06-11

申请号：US16730712

申请日：2019-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/02

Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.

公开(公告)号：US10580685B2

公开(公告)日：2020-03-03

申请号：US16047078

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Hong Yu ,  Laertis Economikos

IPC: H01L23/522 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/764

Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.

公开(公告)号：US20200044034A1

公开(公告)日：2020-02-06

申请号：US16054033

申请日：2018-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laertis Economikos ,  Kevin J. Ryan ,  Ruilong Xie ,  Hui Zang

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/06

Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.

公开(公告)号：US20200020687A1

公开(公告)日：2020-01-16

申请号：US16032108

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Shesh Mani Pandey ,  Jiehui Shu ,  Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Guowei Xu ,  Zhaoying Hu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.

公开(公告)号：US20190393212A1

公开(公告)日：2019-12-26

申请号：US16016058

申请日：2018-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/51 ,  H01L49/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/66

Abstract: A device including RM below the top surface of an HKMG structure, and method of production thereof. Embodiments include first and second HKMG structures over a portion of the substrate and on opposite sides of the STI region, the first and second HKMG structures having a top surface; and a RM over the STI region and between the first and second HKMG structures, wherein the RM is below the top surface of the first and second HKMG structures.

公开(公告)号：US10418285B1

公开(公告)日：2019-09-17

申请号：US15993142

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chun Yu Wong ,  Laertis Economikos

IPC: H01L29/06 ,  H01L21/8234

Abstract: Methods of forming a CT pillar with reduced width and increased distance from neighboring fins and the resulting devices are provided. Embodiments include providing a first pair of fins and a second pair of fins in an oxide layer, wherein the first and second pair of fins include Si; and forming a CT pillar including SiN between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar and distance between the CT pillar and the first and second pair of fins are inversely proportional.