公开(公告)号：US07057997B2

公开(公告)日：2006-06-06

申请号：US10420746

申请日：2003-04-23

Applicant: Henryk Birecki ,  Huei-Pei Kuo ,  Si-Ty Lam ,  Gary A. Gibson

Inventor： Henryk Birecki ,  Huei-Pei Kuo ,  Si-Ty Lam ,  Gary A. Gibson

IPC: G11B7/00

CPC classification number: G11B7/244 ,  B82Y10/00 ,  G11B7/245 ,  G11B9/10 ,  G11B9/14 ,  G11B9/1409 ,  G11B9/149

Abstract: An ultra-high-density data storage device that includes at least one energy beam emitter and a data storage medium that itself includes an organic material. The organic material may include one or more Langmuir-Blodgett layers and may include a conductive polymer. Localized presence or absence of localized disorder in the Langmuir-Blodgett layers may be used to detect data bits formed in the data storage medium. The presence or absence of one-dimensional conductivity in the organic material may also be used to read data bits formed in the data storage medium.

Abstract translation: 一种超高密度数据存储设备，其包括至少一个能量束发射器和本身包括有机材料的数据存储介质。 有机材料可以包括一个或多个Langmuir-Blodgett层，并且可以包括导电聚合物。 Langmuir-Blodgett层中本地化存在或不存在局部紊乱可用于检测在数据存储介质中形成的数据位。 有机材料中存在或不存在一维电导率也可用于读取在数据存储介质中形成的数据位。

公开(公告)号：US06978537B2

公开(公告)日：2005-12-27

申请号：US10459324

申请日：2003-06-10

Applicant: Gary A. Gibson

Inventor： Gary A. Gibson

IPC: H02N1/10 ,  H02N1/12 ,  H01R43/00

CPC classification number: H02N1/10 ,  H02N1/12 ,  Y10S29/90 ,  Y10S977/84 ,  Y10T29/4902 ,  Y10T29/49117 ,  Y10T29/49137

Abstract: A charged species source and a charged species drain are provided. A moveable component is positioned proximate to the charged species source and the charged species drain. A first protrusion and a second protrusion are provided in contact with the moveable component, wherein at least one of the moveable component, the first protrusion and the second protrusion have a size of a micrometer scale or smaller. The moveable component is moved relative to the charged species source and the charged species drain to transfer electrical charge between the source and the drain.

Abstract translation: 提供带电物种源和带电物种排放物。 可移动部件定位成靠近带电物质源和带电物质排出。 第一突起和第二突起设置成与可移动部件接触，其中可移动部件，第一突起和第二突起中的至少一个具有微米级或更小的尺寸。 可移动部件相对于带电物质源和带电物质排出物移动以在源极和漏极之间转移电荷。

公开(公告)号：US06937502B2

公开(公告)日：2005-08-30

申请号：US10617900

申请日：2003-07-10

Applicant: Bao-Sung Bruce Yeh ,  Michael J. Regan ,  Gary A. Gibson

Inventor： Bao-Sung Bruce Yeh ,  Michael J. Regan ,  Gary A. Gibson

IPC: G11C16/02 ,  H01L45/00 ,  G11C11/00

CPC classification number: G11C13/0004 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1213 ,  H01L45/1233 ,  H01L45/143

Abstract: A re-recordable data storage medium is disclosed. The medium in one embodiment includes a phase-changeable layer and an intermediate layer. A junction between the intermediate layer and another layer of the medium provides a conduction barrier under no illumination that is substantially diminished under illumination of the regions of the phase-changeable layer that are in the appropriate phase.

公开(公告)号：US5987588A

公开(公告)日：1999-11-16

申请号：US143344

申请日：1998-08-28

Applicant: Valeri Popescu ,  Merle A. Schultz ,  Gary A. Gibson ,  John E. Spracklen ,  Bruce D. Lightner

Inventor： Valeri Popescu ,  Merle A. Schultz ,  Gary A. Gibson ,  John E. Spracklen ,  Bruce D. Lightner

IPC: G06F9/38 ,  G06F15/00

CPC classification number: G06F9/3855 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.

Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。

公开(公告)号：US5832293A

公开(公告)日：1998-11-03

申请号：US911756

申请日：1997-08-15

Applicant: Valeri Popescu ,  Merle A. Schultz ,  Gary A. Gibson ,  John E. Spracklen ,  Bruce D. Lightner

Inventor： Valeri Popescu ,  Merle A. Schultz ,  Gary A. Gibson ,  John E. Spracklen ,  Bruce D. Lightner

IPC: G06F9/38 ,  G06F9/32

CPC classification number: G06F9/3855 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.

Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。

公开(公告)号：US5708841A

公开(公告)日：1998-01-13

申请号：US710358

申请日：1996-09-17

Applicant: Valeri Popescu ,  Merle A. Schultz ,  Gary A. Gibson ,  John E. Spracklen ,  Bruce D. Lightner

Inventor： Valeri Popescu ,  Merle A. Schultz ,  Gary A. Gibson ,  John E. Spracklen ,  Bruce D. Lightner

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3855 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.

Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。

公开(公告)号：US5561776A

公开(公告)日：1996-10-01

申请号：US469190

申请日：1995-06-06

Applicant: Valeri Popescu ,  Merle A. Schultz ,  Gary A. Gibson ,  John E. Spracklen ,  Bruce D. Lightner

Inventor： Valeri Popescu ,  Merle A. Schultz ,  Gary A. Gibson ,  John E. Spracklen ,  Bruce D. Lightner

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3855 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.

Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。