公开(公告)号：US20120054518A1

公开(公告)日：2012-03-01

申请号：US12868292

申请日：2010-08-25

申请人： Greg Sadowski ,  Stephen David Presant

发明人： Greg Sadowski ,  Stephen David Presant

IPC分类号： G06F1/32 ,  G06F12/00 ,  G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/171

摘要： Circuit and methods provide for adjustable power consumption using a plurality of memory controllers. In one example, a first memory controller has a first power consumption level. A second memory controller has a second power consumption level that differs from the first power consumption level. Memory controller bypass logic is connected to the first and second memory controllers and selects for a memory client at least one of the first and second memory controllers in response to a change in a power conservation condition.

摘要翻译： 电路和方法使用多个存储器控制器提供可调节的功耗。 在一个示例中，第一存储器控制器具有第一功率消耗水平。 第二存储器控制器具有与第一功耗水平不同的第二功率消耗水平。 存储器控制器旁路逻辑被连接到第一和第二存储器控制器，并响应于功率节省条件的变化而为存储器客户端选择第一和第二存储器控制器中的至少一个。

公开(公告)号：US08106804B2

公开(公告)日：2012-01-31

申请号：US12862579

申请日：2010-08-24

申请人： Greg Sadowski ,  George Jacobs ,  Paul Chow

发明人： Greg Sadowski ,  George Jacobs ,  Paul Chow

IPC分类号： H03M1/12

CPC分类号： H04N19/127 ,  H04N19/136 ,  H04N19/172 ,  H04N19/176 ,  H04N19/179 ,  H04N19/42 ,  H04N19/44 ,  H04N19/61

摘要： A video decoder (10) with reduced power consumption includes a power management controller (45) that is operative to select one of a plurality of different power consumption states for a video decoder (10), and, in response to the determination, vary power consumption of at least one operational portion of the video decoder (10). In addition, in one example, a method (200) for reducing power consumption for a video decoder (10) includes determining input stream encoding description data (34) to select one of a plurality of different power consumption states for a video decoder (10) and, in response to the determination, varying power consumption of at least one operational portion of the video decoder (10).

摘要翻译： 具有降低的功耗的视频解码器（10）包括功率管理控制器（45），其可操作以选择视频解码器（10）的多个不同功耗状态中的一个，并且响应于该确定，改变功率 消耗视频解码器（10）的至少一个操作部分。 此外，在一个示例中，用于降低视频解码器（10）的功耗的方法（200）包括确定输入流编码描述数据（34）以选择视频解码器（10）的多个不同功耗状态之一 ），并且响应于所述确定，改变所述视频解码器（10）的至少一个操作部分的功率消耗。

公开(公告)号：US20080232704A1

公开(公告)日：2008-09-25

申请号：US11805988

申请日：2007-05-25

申请人： Greg Sadowski ,  Wai Ki Lo ,  Haibo Liu ,  Stephen Edward Smith ,  Thomas E. Ryan

发明人： Greg Sadowski ,  Wai Ki Lo ,  Haibo Liu ,  Stephen Edward Smith ,  Thomas E. Ryan

IPC分类号： G06K9/36

CPC分类号： H04N19/433 ,  H04N19/423 ,  H04N19/44 ,  H04N19/61

摘要： In one aspect, there is provided a video decoder including a first write port to write uncompressed video data to a first buffer in a first format adapted based on an input required by the video decoder and to suppress writing to the first buffer. The video decoder also includes a second write port to write uncompressed video data to a second buffer in a second format adapted to provide the uncompressed video data for subsequent processing external to the video decoder.

摘要翻译： 一方面，提供了一种视频解码器，包括：第一写入端口，用于以基于视频解码器所需的输入而适应的第一格式将未压缩的视频数据写入第一缓冲器，并且抑制对第一缓冲器的写入。 视频解码器还包括第二写入端口，用于以第二格式将未压缩视频数据写入第二缓冲器，该第二格式适用于提供未压缩的视频数据，用于视频解码器外部的后续处理。

公开(公告)号：US20080180574A1

公开(公告)日：2008-07-31

申请号：US11627757

申请日：2007-01-26

申请人： Greg Sadowski

发明人： Greg Sadowski

IPC分类号： H04N5/445 ,  H04N7/26 ,  G06F3/14

CPC分类号： H04N7/17318 ,  H04N21/4316 ,  H04N21/4728

摘要： A video processing apparatus, for use in a video receiver, includes a decoder configured to decode encoded video information into decoded video information and to output the decoded information, and a configuration module coupled to the decoder and configured to a provide a control signal to the decoder indicative of a reduced-image portion of the video frames to be displayed, where the decoder is configured to respond to the control signal by decoding first macroblocks of the video information within the reduced-image portion and second macroblocks of the video information, in a reference section, adjacent the first macroblocks to account for motion of the images in the reduced-image portion without decoding third macroblocks lying outside of the reduced-image portion and the reference section.

摘要翻译： 一种在视频接收机中使用的视频处理装置包括：解码器，被配置为将经编码的视频信息解码为经解码的视频信息并输出解码的信息，以及配置模块，其耦合到解码器并且被配置为向 指示要显示的视频帧的缩小图像部分的解码器，其中解码器被配置为通过解码视频信息中的视频信息的第一宏块以及视频信息的第二宏块来响应控制信号， 参考部分，与第一宏块相邻以解决缩小图像部分中的图像的运动，而不对位于缩小图像部分和参考部分之外的第三宏块进行解码。

公开(公告)号：US20070176939A1

公开(公告)日：2007-08-02

申请号：US11342985

申请日：2006-01-30

申请人： Greg Sadowski

发明人： Greg Sadowski

IPC分类号： G09G5/36

CPC分类号： G09G5/393 ,  G09G2320/0261 ,  G09G2320/106 ,  G09G2360/121 ,  G09G2360/122

摘要： A system for decoding a video bitstream and a method for replacing image data in a motion prediction cache are described. For each of the cache lines, a tag distance between pixels stored in the cache line and uncached pixels that are to be stored in the cache is calculated. The calculated tag distance is used to determine whether the pixels are outside a local image area defined about the uncached pixels. Pixels determined to be outside the local image area are replaced with the uncached pixels. The motion prediction cache can be organized as sets of cache lines and the method can be performed for each of the cache lines in one of the sets. The definition of the sets can be changed in response to cache performance. Similarly, the local image area can be redefined in response to cache performance.

摘要翻译： 描述用于解码视频比特流的系统和用于替换运动预测高速缓存中的图像数据的方法。 对于每个高速缓存行，计算存储在高速缓存行中的像素和要存储在高速缓存中的未缓存像素之间的标签距离。 计算的标签距离用于确定像素是否在关于未缓冲像素定义的局部图像区域之外。 被确定为在本地图像区域之外的像素被替换为未被缓冲的像素。 运动预测高速缓存可以被组织成高速缓存行集合，并且可以针对其中一个集合中的每个高速缓存线执行该方法。 可以根据缓存性能来更改集合的定义。 类似地，可以响应于高速缓存性能重新定义本地图像区域。

公开(公告)号：US07027072B1

公开(公告)日：2006-04-11

申请号：US09689785

申请日：2000-10-13

申请人： Greg Sadowski

发明人： Greg Sadowski

IPC分类号： G06T17/00

CPC分类号： G06T15/005 ,  G06T2210/52

摘要： A method and system for spatially compositing digital video images with a tile pattern library. Spatial compositing uses a graphics pipeline to render a portion (tile) of each overall frame of digital video images. This reduces the amount of data that each processor must act on and increases the rate at which an overall frame is rendered. Optimization of spatial compositing depends on balancing the processing load among the different pipelines. The processing load typically is a direct function of the size of a given tile and an inverse function of the rendering complexity for objects within this tile. Load balancing strives to measure these variables and adjust, from frame to frame, the number, sizes, and positions of the tiles. The cost of this approach is the necessity to communicate, in conjunction with each frame, the number, sizes, and positions of the tiles. A tile pattern library is a collection of sample compositing windows of various shapes each of which is decomposed into tiles of various shapes and positions. Associated with each sample in the tile pattern library is an index code that can be used to communicate the overall pattern. This reduces the amount of data needed to convey the parameters that define each tile.

摘要翻译： 一种用于将数字视频图像与瓦片图案库进行空间合成的方法和系统。 空间合成使用图形管线来呈现数字视频图像的每个整个帧的部分（瓦片）。 这减少了每个处理器必须作用的数据量，并且增加了渲染整个帧的速率。 空间合成的优化取决于平衡不同管道之间的处理负荷。 处理负载通常是给定块的大小的直接函数，以及该块内的对象的渲染复杂度的反函数。 负载平衡力求测量这些变量，并从帧到帧调整数据块的数量，大小和位置。 这种方法的成本是与每个框架结合使用瓦片的数量，尺寸和位置的必要性。 瓦片图案库是各种形状的样本合成窗口的集合，每个窗口都被分解成各种形状和位置的瓦片。 与瓦片图案库中的每个样本相关联的是可用于传达整体图案的索引代码。 这减少了传达定义每个瓦片的参数所需的数据量。

公开(公告)号：US6160589A

公开(公告)日：2000-12-12

申请号：US998979

申请日：1997-12-29

申请人： Greg Sadowski

发明人： Greg Sadowski

IPC分类号： H04N5/10 ,  H04N5/08 ,  H04N5/46

CPC分类号： H04N5/10

摘要： A video frame detector circuit used in synchronizing one video signal with another video signal. The video frame detector of the present invention is able to automatically detect a start of frame portion of any video composite synchronization signal connected to it without requiring programming. The start of frame commences with the least frequent vertical field, or if all fields are equally frequent, a deterministic process is used to promote one of the fields to be the start of the frame. Since the video frame detector circuit of the present invention does not require programming to recognize various video signal formats, it readily adapts to different video signal conditions with little or no manual intervention. The video frame detector contains a number of memory stores for storing previously detected video patterns obtained from a composite synchronization signal. Once a current pattern is ascertained from the composite synchronization signal, it is compared against the stored patterns. Information regarding recognized patterns is stored in a history FIFO. New patterns are stored in vacant memories replacing those stored patterns that are most frequently seen. Frequency counters maintain information as to the frequency of each stored pattern. A state machine assumes that the least frequently ascertained patterns are the start of frame portion and generates a start of frame pulse accordingly. The start of frame pulse can be delayed to properly align with the video signal.

摘要翻译： 用于使一个视频信号与另一个视频信号同步的视频帧检测器电路。 本发明的视频帧检测器能够自动地检测与其连接的任何视频复合同步信号的帧部分的开始，而不需要编程。 帧的开始始于最不频繁的垂直场，或者如果所有场同样频繁，则使用确定性过程来将其中一个场作为帧的开始。 由于本发明的视频帧检测器电路不需要编程来识别各种视频信号格式，所以它很容易地适应不同的视频信号条件，很少或没有手动干预。 视频帧检测器包含多个用于存储从复合同步信号获得的先前检测到的视频模式的存储器存储。 一旦从复合同步信号确定当前模式，就将其与存储的模式进行比较。 关于识别的模式的信息存储在历史FIFO中。 新的模式存储在空闲的存储器中，代替最常见的存储模式。 频率计数器保持关于每个存储模式的频率的信息。 状态机假设最不频繁地确定的模式是帧部分的开始并且相应地产生帧脉冲的开始。 可以延迟帧脉冲的开始以与视频信号正确对齐。

公开(公告)号：US20170090957A1

公开(公告)日：2017-03-30

申请号：US14865731

申请日：2015-09-25

申请人： Greg Sadowski ,  Wayne Burleson ,  Indrani Paul ,  Manish Arora

发明人： Greg Sadowski ,  Wayne Burleson ,  Indrani Paul ,  Manish Arora

IPC分类号： G06F9/445 ,  G06F1/26 ,  G06F13/42

CPC分类号： G06F9/44505 ,  G06F1/26 ,  G06F1/266 ,  G06F9/3869 ,  G06F9/3887 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

摘要： Various integrated circuits and methods of making and operating the same are disclosed. In aspect, a method of operating an integrated circuit is provided. The method includes, in a compute unit that has a first lane and a second lane, executing operations with the first lane and the second lane. The first lane and the second lane are monitored for an indicator of asynchronous operation. An input voltage of one or both of the first lane and the second lane is selectively adjusted if the indicator of asynchronous operation is detected.

公开(公告)号：US09582060B2

公开(公告)日：2017-02-28

申请号：US11469326

申请日：2006-08-31

申请人： Aris Balatsos ,  Kevin O'Neil ,  Greg Sadowski

发明人： Aris Balatsos ,  Kevin O'Neil ,  Greg Sadowski

IPC分类号： G06F1/00 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

摘要： A device includes a processor that is operative to process a data stream such as executable code, encoded video or other suitable data stream, and has a plurality of processor portions. The device further includes a power management controller coupled to the processor portions that controls power consumption of the processor portions based on application profile data associated with the data stream. The application profile data may be included with executable code or provided separately and may directly indicate usage/nonusage of portions of the processor or the data stream may have inherent application profile data in the header that indirectly identifies usage of the processor portions.

摘要翻译： 一种设备包括可操作以处理诸如可执行代码，编码视频或其他合适数据流之类的数据流的处理器，并且具有多个处理器部分。 该设备还包括耦合到处理器部分的功率管理控制器，其基于与数据流相关联的应用简档数据来控制处理器部分的功率消耗。 应用程序简档数据可以包括可执行代码或单独提供，并且可以直接指示处理器的部分的使用/不使用，或者数据流可以在头部中具有间接标识处理器部分的使用的固有应用简档数据。

公开(公告)号：US08799685B2

公开(公告)日：2014-08-05

申请号：US12868292

申请日：2010-08-25

申请人： Greg Sadowski ,  Stephen David Presant

发明人： Greg Sadowski ,  Stephen David Presant

IPC分类号： G06F1/00 ,  G06T1/60 ,  G09G5/39

CPC分类号： G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/171

摘要： Circuit and methods provide for adjustable power consumption using a plurality of memory controllers. In one example, a first memory controller has a first power consumption level. A second memory controller has a second power consumption level that differs from the first power consumption level. Memory controller bypass logic is connected to the first and second memory controllers and selects for a memory client at least one of the first and second memory controllers in response to a change in a power conservation condition.

摘要翻译： 电路和方法使用多个存储器控制器提供可调节的功耗。 在一个示例中，第一存储器控制器具有第一功率消耗水平。 第二存储器控制器具有与第一功耗水平不同的第二功率消耗水平。 存储器控制器旁路逻辑被连接到第一和第二存储器控制器，并响应于功率节省条件的变化而为存储器客户端选择第一和第二存储器控制器中的至少一个。