公开(公告)号：US06515508B1

公开(公告)日：2003-02-04

申请号：US09853439

申请日：2001-05-10

申请人： Wanli Chang ,  Andy Lee ,  Cameron McClintock ,  Richard Cliff ,  Richard Yen-Hsiang Chang

发明人： Wanli Chang ,  Andy Lee ,  Cameron McClintock ,  Richard Cliff ,  Richard Yen-Hsiang Chang

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K5/151 ,  H03K19/01721 ,  H03K19/17784

摘要： At least some of the interconnection signaling on a programmable logic device (“PLD”) is by differential signaling using differential driver circuitry to apply differential signals to a pair of conductors that extend to differential receiver circuitry. Such differential interconnection signaling helps the PLD operate satisfactorily with lower power supply voltages. The conductors in each differential signaling pair may cross over one another at various intervals in order to help reduce the adverse effects of capacitive coupling between adjacent and parallel signaling paths.

摘要翻译： 可编程逻辑器件（“PLD”）上的至少一些互连信号通过使用差分驱动器电路的差分信号来将差分信号施加到延伸到差分接收器电路的一对导体。 这种差分互连信令有助于PLD在较低的电源电压下令人满意地工作。 每个差分信号对中的导体可以以不同的间隔彼此交叉，以便有助于减少相邻和并行信令路径之间的电容耦合的不利影响。

公开(公告)号：US06459303B1

公开(公告)日：2002-10-01

申请号：US09829499

申请日：2001-04-09

申请人： Wanli Chang ,  David Jefferson

发明人： Wanli Chang ,  David Jefferson

IPC分类号： H03K19082

CPC分类号： G11C8/10

摘要： A high-performance address decoder circuit provides higher speed read and write access for an embedded memory of a programmable logic integrated circuit. The address decoder is programmable to allow addressing of the memory in different data widths and depths. The circuitry can be used as column address decoder or row address decoder, or both. In a dual-port memory implementation of the memory, there can be two instances of each of the decoders, one for writing and one for reading.

摘要翻译： 高性能地址解码器电路为可编程逻辑集成电路的嵌入式存储器提供更高速度的读和写访问。 地址解码器是可编程的，以允许以不同的数据宽度和深度寻址存储器。 电路可以用作列地址解码器或行地址解码器，或两者兼有。 在存储器的双端口存储器实现中，每个解码器可以有两个实例，一个用于写入，一个用于读取。

公开(公告)号：US5802540A

公开(公告)日：1998-09-01

申请号：US555283

申请日：1995-11-08

申请人： Chiakang Sung ,  Joseph Huang ,  Wanli Chang

发明人： Chiakang Sung ,  Joseph Huang ,  Wanli Chang

IPC分类号： G11C8/04 ,  G11C8/12 ,  H03K19/177 ,  G06F12/02

CPC分类号： G11C8/04 ,  G11C8/12 ,  H03K19/17704 ,  H03K19/1776 ,  H03K19/17764

摘要： A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, the address decoder that is normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter or other similar coded address signal generating circuitry is used to supply address information to the decoder.