公开(公告)号：US08598675B2

公开(公告)日：2013-12-03

申请号：US13024577

申请日：2011-02-10

申请人： Shiang-Bau Wang

发明人： Shiang-Bau Wang

IPC分类号： H01L21/70

CPC分类号： H01L29/0649 ,  H01L21/76232

摘要： An trench isolation structure and method for manufacturing the trench isolation structure are disclosed. An exemplary trench isolation structure includes a first portion and a second portion. The first portion extends from a surface of a semiconductor substrate to a first depth in the semiconductor substrate, and has a width that tapers from a first width at the surface of the semiconductor substrate to a second width at the first depth, the first width being greater than the second width. The second portion extends from the first depth to a second depth in the semiconductor substrate, and has substantially the second width from the first depth to the second depth.

摘要翻译： 公开了用于制造沟槽隔离结构的沟槽隔离结构和方法。 示例性的沟槽隔离结构包括第一部分和第二部分。 第一部分从半导体衬底的表面延伸到半导体衬底中的第一深度，并且具有从半导体衬底的表面处的第一宽度到第一深度处的第二宽度渐缩的宽度，第一宽度为 大于第二宽度。 第二部分从半导体衬底中的第一深度延伸到第二深度，并且具有从第一深度到第二深度的基本上第二宽度。

公开(公告)号：US08518786B2

公开(公告)日：2013-08-27

申请号：US13744540

申请日：2013-01-18

申请人： Shiang-Bau Wang

发明人： Shiang-Bau Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/42372 ,  H01L29/66628 ,  H01L29/66636

摘要： A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching step to define the pillars, an epitaxial silicon film is grown on the substrate between the pillars prior to forming recesses in the substrate for the source/drain regions of the transistor. The epitaxial silicon film compensates for substrate material that may be lost during formation of the gate electrode pillars, thereby producing source/drain recesses having a configuration amenable to be filled uniformly with silicon for later forming the source/drain regions in the substrate.

摘要翻译： 一种形成诸如MOSFET的半导体器件的方法。 该方法包括通过材料沉积和蚀刻在硅衬底上形成栅电极柱。 在蚀刻步骤定义柱之后，在用于晶体管的源/漏区的衬底中形成凹陷之前，在柱之间的衬底上生长外延硅膜。 外延硅膜补偿在栅极电极柱形成期间可能损失的衬底材料，从而产生具有适于被均匀填充硅的构造的源极/漏极凹槽，以用于在衬底中形成源极/漏极区域。

公开(公告)号：US06652712B2

公开(公告)日：2003-11-25

申请号：US10028646

申请日：2001-12-19

申请人： Shiang-Bau Wang ,  Daniel J. Hoffman ,  Chunshi Cui ,  Yan Ye ,  Gerardo Delgadino ,  David McParland ,  Matthew L. Miller ,  Douglas A. Buchberger, Jr. ,  Steven C. Shannon

发明人： Shiang-Bau Wang ,  Daniel J. Hoffman ,  Chunshi Cui ,  Yan Ye ,  Gerardo Delgadino ,  David McParland ,  Matthew L. Miller ,  Douglas A. Buchberger, Jr. ,  Steven C. Shannon

IPC分类号： C23C1600

CPC分类号： H01J37/321

摘要： An inductive antenna of a plasma reactor for processing a semiconductor wafer is connected to a radio frequency (RF) power source, and consists of a conductor arranged in successive loops that wind in opposing directions, adjacent pairs of the successive loops having facing portions in which current flow is parallel, the facing portions being sufficiently close to at least nearly share a common current path, whereby to form transitions across the facing portions between opposing magnetic polarizations.

摘要翻译： 用于处理半导体晶片的等离子体反应器的感应天线连接到射频（RF）电源，并且由布置在相反方向上的连续回路中的导体组成，相邻的一对连续的回路具有面对部分 电流流动是平行的，面对部分足够接近至少几乎共享公共电流路径，从而在相对的磁极化之间跨越相对部分形成过渡。

公开(公告)号：US06201208B1

公开(公告)日：2001-03-13

申请号：US09433461

申请日：1999-11-04

申请人： Amy Eileen Wendt ,  Shiang-Bau Wang

发明人： Amy Eileen Wendt ,  Shiang-Bau Wang

IPC分类号： B23K900

CPC分类号： H01J37/32082 ,  B23K10/003 ,  B23K2101/40 ,  H01J37/32706 ,  H01L21/31116

摘要： In plasma processing, a bias voltage is provided from a power supply through a DC blocking capacitor to a platform on which a substrate to be treated is supported within a plasma reactor. The periodic bias voltage applied to the DC blocking capacitor has a waveform comprised of a voltage pulse peak followed by a ramp down of voltage from a first level lower than the pulse peak to a second lower level, the period of the bias waveform and the ramp down of voltage in each cycle selected to compensate for and substantially cancel the effect of ion accumulation on the substrate so as to maintain a substantially constant DC self-bias voltage on the substrate between the voltage pulse peaks. The waveform may include a single voltage pulse peak followed by a ramp down in voltage during each cycle of the bias voltage such that the ion energy distribution function at the substrate has a single narrow peak centered at a selected ion energy. The waveform may also comprise two voltage pulse peaks each followed by a ramp down of voltage selected to provide a bias voltage at the substrate comprising two voltage peaks during each cycle with DC self-bias voltages following each pulse peak at two different substantially constant DC levels, resulting in an ion energy distribution function at the substrate that includes two peaks of ion flux centered at two selected ion energies with substantially no ion flux at other ion energies. The ion energy distribution function may thus be tailored to best accommodate the desired plasma treatment process and can be used to reduce the effects of differential charging of substrates.

摘要翻译： 在等离子体处理中，从电源通过隔直流电容器向待处理的基板支撑在等离子体反应器内的平台提供偏置电压。 施加到隔直电容器的周期性偏置电压具有波形，其包括电压脉冲峰值，随后是从低于脉冲峰值的第一电平到第二较低电平的电压斜坡下降，偏置波形和斜坡的周期 选择每个循环中的电压降低以补偿并基本上消除基板上的离子累积的影响，以便在电压脉冲峰值之间保持基板上的基本恒定的DC自偏压。 波形可以包括单个电压脉冲峰值，随后在偏置电压的每个周期期间电压下降，使得衬底处的离子能量分布函数具有以所选离子能为中心的单个窄峰值。 波形还可以包括两个电压脉冲峰值，每个电压脉冲峰值随后是选择的电压的斜坡下降，以在每个周期期间提供包括两个电压峰值的偏置电压，其中在两个不同的基本恒定的DC电平处的每个脉冲峰值之后的直流自偏压 导致在衬底处的离子能量分布函数，其包括以两个选择的离子能量为中心的离子通量的两个峰值，其它离子能量基本上没有离子通量。 因此，离子能量分布函数可以被定制以最佳地适应期望的等离子体处理过程，并且可以用于减少衬底的不同充电的影响。

公开(公告)号：US09142462B2

公开(公告)日：2015-09-22

申请号：US13278569

申请日：2011-10-21

申请人： Shiang-Bau Wang

发明人： Shiang-Bau Wang

IPC分类号： H01L21/3205 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/42368 ,  H01L21/76834 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/528 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit structure includes providing a gate stack and a gate spacer on a sidewall of the gate stack. A contact etch stop layer (CESL) is formed overlying the gate spacer and the gate stack. The CESL includes a top portion over the gate stack, a bottom portion lower than the top portion, and a sidewall portion over a sidewall of the gate spacer. The top and bottom portions are spaced apart from each other by the sidewall portion. The sidewall portion has a thickness less than a thickness of the top portion or a thickness of the bottom portion.

摘要翻译： 形成集成电路结构的方法包括在栅极叠层的侧壁上设置栅极堆叠和栅极间隔物。 接触蚀刻停止层（CESL）形成在栅极间隔物和栅极堆叠之上。 CESL包括在栅极叠层上的顶部，比顶部低的底部部分，以及在栅极间隔物的侧壁上方的侧壁部分。 顶部和底部通过侧壁部彼此间隔开。 侧壁部分的厚度小于顶部的厚度或底部的厚度。

公开(公告)号：US20120205774A1

公开(公告)日：2012-08-16

申请号：US13024577

申请日：2011-02-10

申请人： Shiang-Bau Wang

发明人： Shiang-Bau Wang

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L29/0649 ,  H01L21/76232

摘要： An trench isolation structure and method for manufacturing the trench isolation structure are disclosed. An exemplary trench isolation structure includes a first portion and a second portion. The first portion extends from a surface of a semiconductor substrate to a first depth in the semiconductor substrate, and has a width that tapers from a first width at the surface of the semiconductor substrate to a second width at the first depth, the first width being greater than the second width. The second portion extends from the first depth to a second depth in the semiconductor substrate, and has substantially the second width from the first depth to the second depth.

摘要翻译： 公开了用于制造沟槽隔离结构的沟槽隔离结构和方法。 示例性的沟槽隔离结构包括第一部分和第二部分。 第一部分从半导体衬底的表面延伸到半导体衬底中的第一深度，并且具有从半导体衬底的表面处的第一宽度到第一深度处的第二宽度渐缩的宽度，第一宽度为 大于第二宽度。 第二部分从半导体衬底中的第一深度延伸到第二深度，并且具有从第一深度到第二深度的基本上第二宽度。

公开(公告)号：US06667577B2

公开(公告)日：2003-12-23

申请号：US10025408

申请日：2001-12-18

申请人： Steven Shannon ,  Daniel Hoffman ,  Chunshi Cui ,  Yan Ye ,  Gerardo Delgadino ,  Douglas A. Buchberger, Jr. ,  Shiang-Bau Wang ,  Robert B. Hagen ,  Matthew L Miller ,  Stephen Thai

发明人： Steven Shannon ,  Daniel Hoffman ,  Chunshi Cui ,  Yan Ye ,  Gerardo Delgadino ,  Douglas A. Buchberger, Jr. ,  Shiang-Bau Wang ,  Robert B. Hagen ,  Matthew L Miller ,  Stephen Thai

IPC分类号： H01J724

CPC分类号： H01J37/321

摘要： An RF power applicator of the reactor includes inner and outer conductive radial spokes. The set of inner conductive spokes extends radially outwardly from and is electrically connected to the conductive post toward the conductive side wall. The set of outer conductive spokes extends radially inwardly toward the conductive post from and is electrically connected to the conductive side wall. In this way, the inner and outer sets of conductive spokes are electrically connected together, the combination of the inner and outer set of spokes with the conductive enclosure having a fundamental resonant frequency inversely proportional to the height of the conductive enclosure and the lengths of the inner and outer set of conductive spokes. An RF source power generator is coupled across the RF power applicator and has an RF frequency corresponding to the fundamental resonant frequency.

摘要翻译： 反应器的RF功率施加器包括内部和外部导电的径向辐条。 一组内导电轮辐径向向外延伸并且与导电柱电连接到导电侧壁。 一组外导电轮辐径向向内延伸到导电柱，并与导电侧壁电连接。 以这种方式，导电辐条的内部和外部组电连接在一起，内部和外部组的辐条与导电外壳的组合具有与导电外壳的高度成反比的基本谐振频率和 内外套导电辐条。 RF源功率发生器耦合在RF功率施加器上并且具有对应于基本谐振频率的RF频率。