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    Method for fabricating a semiconductor product with a memory area and a logic area
    31.
    发明授权
    Method for fabricating a semiconductor product with a memory area and a logic area 有权
    用于制造具有存储区域和逻辑区域的半导体产品的方法

    公开(公告)号：US07217610B2

    公开(公告)日：2007-05-15

    申请号：US10485308

    申请日：2002-07-30

    申请人： Werner Graf ,  Albrecht Kieslich

    发明人： Werner Graf ,  Albrecht Kieslich

    IPC分类号： H01L21/8238 ,  H01L27/108

    CPC分类号： H01L27/10894 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10873

    摘要： A method for the integration of field-effect transistors for memory and logic applications in a semiconductor substrate is disclosed. The gate dielectric and a semiconductor layer are deposited over the whole area both in the logic region and in the memory region. From these layers, the gate electrodes in the memory region are formed, the source and drain regions are implanted and the memory region is covered in a planarizing manner with an insulation material. Afterward, the gate electrodes are formed from the semiconductor layer and the gate dielectric in the logic region.

    摘要翻译： 公开了用于在半导体衬底中集成用于存储器和逻辑应用的场效应晶体管的方法。 栅极电介质和半导体层沉积在逻辑区域和存储区域中的整个区域上。 从这些层，形成存储区域中的栅电极，注入源区和漏区，并且用绝缘材料以平坦化方式覆盖存储区。 之后，栅极电极由逻辑区域中的半导体层和栅极电介质形成。

    Method of treating a structured surface
    32.
    发明申请
    Method of treating a structured surface 有权
    处理结构化表面的方法

    公开(公告)号：US20060172539A1

    公开(公告)日：2006-08-03

    申请号：US11043950

    申请日：2005-01-28

    申请人： Matthias Kroenke ,  Thomas Dittkrist ,  Werner Graf

    发明人： Matthias Kroenke ,  Thomas Dittkrist ,  Werner Graf

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31053

    摘要： The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A plurality of layers is deposited on said surface wherein a lower layer exhibits a higher polishing rate than an upper layer and wherein the thickness of the plurality of layers exceeds the step height. Afterwards the plurality of layers is chemically mechanically polished such that the lower layer is at least partly removed in the first region. By this method achieves a better planarisation. Additionally, smaller top contact openings after a wet clean step are achievable and a deformation of contact openings due to annealing steps is reduced.

    摘要翻译： 本发明提供了一种处理结构化表面的简单方法，该结构化表面包括在第二区域中的第一区域和下表面中的较高表面。 多个层沉积在所述表面上，其中下层表现出比上层更高的抛光速率，并且其中多个层的厚度超过台阶高度。 之后，多层被化学机械抛光，使得下层在第一区域中被至少部分去除。 通过这种方法实现更好的平面化。 此外，可以实现在湿式清洁步骤之后较小的顶部接触开口，并且由于退火步骤导致的接触开口的变形减小。

    Process for preparing acyloxysilanes and acyloxysiloxanes
    36.
    发明授权
    Process for preparing acyloxysilanes and acyloxysiloxanes 失效
    制备酰氧基硅烷和酰氧基硅氧烷的方法

    公开(公告)号：US4176130A

    公开(公告)日：1979-11-27

    申请号：US974200

    申请日：1978-12-28

    申请人： Peter John ,  Wolfgang Feichtner ,  Werner Graf ,  Volker Frey

    发明人： Peter John ,  Wolfgang Feichtner ,  Werner Graf ,  Volker Frey

    IPC分类号： C07F7/08 ,  C07F7/18

    CPC分类号： C07F7/1896 ,  C07F7/0874 ,  C07F7/0885

    摘要： This invention relates to an improved process for preparing acyloxysilanes and acyloxysiloxanes which comprises conducting an aliphatic carboxylic acid in vapor form upwards from the bottom of a column countercurrent to the flow of a chlorosilane in which the carboxylic acid is introduced into the column at such a rate that the carboxylic acid does not exceed about 1.3 mol per gram atom of Si-bonded chlorine in the column while removing the acyloxysilane from the bottom of the column.The acyloxysiloxanes are prepared by conducting an aliphatic carboxylic acid upwards from the bottom of a column in vapor form countercurrent to the flow of a chlorosilane while introducing up to about 10 percent by weight of water based on the weight of the carboxylic acid into the column and removing the acyloxysiloxane from the bottom of the column.

    摘要翻译： 本发明涉及一种制备酰氧基硅烷和酰氧基硅氧烷的改进方法，其包括将蒸气形式的脂族羧酸从塔的底部向上与氯代硅烷的流动逆流相接触，其中羧酸以这样的速率引入塔中 羧酸在柱中不超过约1.3mol /克原子的Si键合氯，同时从柱底除去酰氧基硅烷。 酰氧基硅氧烷是通过以与氯硅烷流相反的蒸气形式从塔底向上导入脂族羧酸而制备的，同时基于羧酸重量加入到塔中约10重量％的水， 从柱的底部除去酰氧基硅氧烷。

    Process for reacting nitric oxide with hydrogen
    37.
    发明授权
    Process for reacting nitric oxide with hydrogen 失效
    一氧化氮与氢反应的方法

    公开(公告)号：US3954946A

    公开(公告)日：1976-05-04

    申请号：US489621

    申请日：1974-07-18

    申请人： Werner Graf ,  Johann Karl Forrer

    发明人： Werner Graf ,  Johann Karl Forrer

    IPC分类号： B01D19/00 ,  C01B21/14

    CPC分类号： C01B21/1418 ,  B01D19/0068

    摘要： Method and apparatus for reacting nitric oxide with H.sub.2 in the presence of noble metal catalysts in which waste gas is obtained by separating the gas contained in a liquid medium flowing countercurrently to the bubbles in a counter-current bubble column. Preferably, only a portion of the separated gas is removed as waste gas, the remainder being recycled. The apparatus comprises a counter-current bubble column having a gas recycling circuit to permit the recycling of excess NO contained in the separated gas.

    摘要翻译： 在贵金属催化剂存在下使一氧化氮与氢气反应的方法和装置，其中废气通过在逆流气泡塔中与气泡逆流流动的液体介质中分离出来的气体而获得。 优选地，仅将一部分分离的气体作为废气除去，其余部分被再循环。 该装置包括具有气体回收回路的逆流鼓泡塔，以允许再循环分离气体中所含的过量的NO。

    Energy storage device and method for storing energy
    38.
    发明授权
    Energy storage device and method for storing energy 有权

    公开(公告)号：US10280803B2

    公开(公告)日：2019-05-07

    申请号：US15568685

    申请日：2016-04-19

    申请人： Peter Ortmann ,  Werner Graf

    发明人： Peter Ortmann ,  Werner Graf

    IPC分类号： F01K3/00 ,  F01K25/00 ,  F01K3/06 ,  F01K3/12

    摘要： An energy storage device for storing energy including: a high-temperature regenerator containing a storage material and a working gas as heat transfer medium for the purpose of exchanging heat between the storage material and the traversing working gas, a closed charging circuit for the working gas, including a first compressor, a first expander, a first recuperator having a first and a second heat exchange duct, the high-temperature regenerator and a pre-heater, wherein the first compressor is coupled to the first expander by a shaft, a discharging circuit for the working gas, and including a switch that selectively connects the high-temperature regenerator to either the charging circuit or the discharging circuit, such that the circuit containing the high-temperature regenerator forms a closed circuit.

    Word Line to Bit Line Spacing Method and Apparatus
    39.
    发明申请
    Word Line to Bit Line Spacing Method and Apparatus 有权
    字线对位线间距法和装置

    公开(公告)号：US20090302380A1

    公开(公告)日：2009-12-10

    申请号：US12134740

    申请日：2008-06-06

    申请人： Werner Graf ,  Lars Heineck ,  Martin Popp

    发明人： Werner Graf ,  Lars Heineck ,  Martin Popp

    IPC分类号： H01L27/105 ,  H01L21/762

    CPC分类号： H01L21/76232 ,  H01L21/743 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891

    摘要： In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.

    摘要翻译： 在一个实施例中，存储单元包括布置在半导体衬底中的位线和布置在位线附近的位线接触区域。 在形成在半导体衬底中的沟槽中的位线接触区域上方布置字线。 大致U形绝缘层布置在沟槽的底部区域中，并将位线和位线接触区域与字线分离。

    Method for producing a semiconductor structure
    40.
    发明授权
    Method for producing a semiconductor structure 有权
    半导体结构的制造方法

    公开(公告)号：US07314803B2

    公开(公告)日：2008-01-01

    申请号：US11282432

    申请日：2005-11-18

    申请人： Werner Graf ,  Lars Heineck ,  Jana Horst

    发明人： Werner Graf ,  Lars Heineck ,  Jana Horst

    IPC分类号： H01L21/336 ,  H01L21/461 ,  H01L21/302

    CPC分类号： H01L27/105 ,  H01L27/1052

    摘要： In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

    摘要翻译： 在制造半导体结构的方法中，提供了具有顶表面的衬底的半导体。 栅极电介质层设置在顶表面上，并且在栅极介电层上提供有具有第一多个栅极堆叠的存储单元阵列区域和具有第二多个栅极堆叠的外围元件区域。 在存储单元阵列区域和外围元件区域上提供介电层。 执行存储单元阵列区域和外围元件区域上的第一源极/漏极注入，形成存储单元阵列区域上的阻挡掩模，使用阻挡掩模去除电介质层，并且使用第二源极/漏极注入 在存储单元阵列区域和外围元件区域上进行，其中存储单元阵列区域被掩模保护。