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63 条记录 (耗时 0.026 秒)

    Gate-array type intergated circuit semiconductor device
    34.
    发明授权
    Gate-array type intergated circuit semiconductor device 失效
    门阵列型中间电路半导体器件

    公开(公告)号：US4984050A

    公开(公告)日：1991-01-08

    申请号：US297628

    申请日：1989-01-13

    申请人： Masaharu Kobayashi

    发明人： Masaharu Kobayashi

    IPC分类号： H01L21/768 ,  H01L21/82 ,  H01L23/522 ,  H01L27/118

    CPC分类号： H01L27/11801 ,  H01L2924/0002 ,  Y10S257/903 ,  Y10S257/906

    摘要： A gate array type integrated circuit semiconductor device includes a semiconductor substrate, in a basic cell forming portion of which are formed a plurality of impurity regions of basic circuit elements. The impurity regions form a plurality of basic cells. A field insulating layer is also formed on the substrate, which is partially embedded in the major surface of the substrate and is formed entirely on a wiring channel forming portion of the substrate and selectively on the basic cell forming portion of the same to surround each of the impurity regions. An insulating film is formed on the field insulating layer. A wiring structure is provided, which includes mutual wirings formed of a first level conductive layer, internal wirings, and interconnecting wirings formed of a second level conductive layer higher than the first level conductive layer. Each of the mutual wirings is formed only on the insulating film formed on the wiring channel forming portion and is connected to the impurity regions through the interconnecting and internal wirings.

    摘要翻译： 门阵列型集成电路半导体器件包括半导体衬底，其基本单元形成部分形成有多个基本电路元件的杂质区域。 杂质区形成多个碱性电池。 场致绝缘层也形成在衬底上，该衬底被部分地嵌入衬底的主表面中，并且整体地形成在衬底的布线沟道形成部分上，并且选择性地在其基本单元形成部分上围绕 杂质区。 在场绝缘层上形成绝缘膜。 提供一种布线结构，其包括由第一层导电层，内部布线和由比第一层导电层高的第二层导电层形成的互连布线形成的互连。 每个相互配线仅形成在形成在布线沟道形成部分上的绝缘膜上，并且通过互连和内部布线连接到杂质区域。

    Thermoplastic resin composition having low permittivity, prepreg, laminated plate and laminated material for circuit using the same
    37.
    发明授权
    Thermoplastic resin composition having low permittivity, prepreg, laminated plate and laminated material for circuit using the same 失效
    具有低介电常数的热塑性树脂组合物，预浸料，层压板和使用其的电路层压材料

    公开(公告)号：US06492030B1

    公开(公告)日：2002-12-10

    申请号：US09647217

    申请日：2000-09-28

    申请人： Takeshi Hashimoto ,  Masaharu Kobayashi ,  Takeshi Sato ,  Daisuke Orino

    发明人： Takeshi Hashimoto ,  Masaharu Kobayashi ,  Takeshi Sato ,  Daisuke Orino

    IPC分类号： B32B904

    CPC分类号： H05K1/0346 ,  C08G73/10 ,  C08G73/1039 ,  C08G73/106 ,  C08G73/1064 ,  C08G73/12 ,  C08G73/125 ,  H01B3/306 ,  H01B3/465 ,  Y10T428/31663 ,  Y10T428/31721

    摘要： The present invention relates to a thermosetting low dielectric resin composition, a laminate for use in printed wiring, a laminate for a circuit, and the like. The present invention's thermosetting low dielectric resin composition contains a specific siloxane denatured polyimide, a compound having two or more allyl or methylallyl groups, and a compound having two or more maleimide groups. This resin composition adheres extremely well to metals with a low dielectric constant and low dielectric dissipation factor, and demonstrates very little scattering of the resin during operational processes like punching or cutting. By using laminates or laminates for circuits that employ this resin composition, electrical signals can be propagated more quickly, enabling signals to be processed at faster speeds. In addition, the present invention can be applied to the formation of miniaturized circuit wiring, and is suitably employed in electronic devices employed in the high frequency region, and, in particular, in electronic devices that must be made smaller and lighter in weight.

    摘要翻译： 本发明涉及一种热固性低电介质树脂组合物，用于印刷布线的叠层体，电路用层压体等。 本发明的热固性低介电性树脂组合物含有特定的硅氧烷改性聚酰亚胺，具有2个以上烯丙基或甲基烯丙基的化合物和具有2个以上马来酰亚胺基的化合物。 该树脂组合物非常好地粘附在具有低介电常数和低介电损耗因子的金属上，并且在诸如冲压或切割的操作过程中表现出非常小的树脂散射。 通过对采用这种树脂组合物的电路使用层压板或层压板，可以更迅速地传播电信号，从而能够以更快的速度处理信号。 此外，本发明可以应用于形成小型化的电路布线，并且适用于在高频区域中使用的电子设备中，特别是在必须制造得更小更轻的电子设备中。

    Manufacture of semiconductor device using A-C anti-reflection coating
    38.
    发明授权
    Manufacture of semiconductor device using A-C anti-reflection coating 失效
    使用A-C抗反射涂层制造半导体器件

    公开(公告)号：US06420095B1

    公开(公告)日：2002-07-16

    申请号：US09466830

    申请日：1999-12-20

    申请人： Eiichi Kawamura ,  Teruyoshi Yao ,  Nobuhisa Naori ,  Koichi Hashimoto ,  Masaharu Kobayashi ,  Tadasi Oshima

    发明人： Eiichi Kawamura ,  Teruyoshi Yao ,  Nobuhisa Naori ,  Koichi Hashimoto ,  Masaharu Kobayashi ,  Tadasi Oshima

    IPC分类号： G03F700

    CPC分类号： G03F7/091

    摘要： A method of manufacturing a semiconductor device including the steps of: forming a transparent oxide film on a light reflecting surface; forming an anti-reflective a-c film on the surface of the transparent film; and coating a photoresist film on the surface of the anti-reflective film and patterning the photoresist film, wherein the thicknesses of the anti-reflective film and the transparent film are selected so as to set a standing wave intensity Isw=I&dgr;/Iave to 0.2 or smaller, where Iave is an average value of light intensity in the photoresist film, and I&dgr; is an amplitude of a light intensity change. A fine pattern can be formed on a highly reflective substrate with a small size variation and at a high precision.

    摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在光反射表面上形成透明氧化膜; 在透明膜的表面上形成抗反射性的a-c膜; 并在抗反射膜的表面上涂覆光致抗蚀剂膜并对抗蚀剂膜进行构图，其中选择抗反射膜和透明膜的厚度，以将驻波强度Isw = Idelta / Iave设定为0.2 或更小，其中Iave是光致抗蚀剂膜中的光强度的平均值，Idelta是光强度变化的幅度。 可以在具有小尺寸变化和高精度的高反射性基板上形成精细图案。