Thermoplastic resin composition having low permittivity, prepreg, laminated plate and laminated material for circuit using the same
    2.
    发明授权
    Thermoplastic resin composition having low permittivity, prepreg, laminated plate and laminated material for circuit using the same 失效
    具有低介电常数的热塑性树脂组合物,预浸料,层压板和使用其的电路层压材料

    公开(公告)号:US06492030B1

    公开(公告)日:2002-12-10

    申请号:US09647217

    申请日:2000-09-28

    IPC分类号: B32B904

    摘要: The present invention relates to a thermosetting low dielectric resin composition, a laminate for use in printed wiring, a laminate for a circuit, and the like. The present invention's thermosetting low dielectric resin composition contains a specific siloxane denatured polyimide, a compound having two or more allyl or methylallyl groups, and a compound having two or more maleimide groups. This resin composition adheres extremely well to metals with a low dielectric constant and low dielectric dissipation factor, and demonstrates very little scattering of the resin during operational processes like punching or cutting. By using laminates or laminates for circuits that employ this resin composition, electrical signals can be propagated more quickly, enabling signals to be processed at faster speeds. In addition, the present invention can be applied to the formation of miniaturized circuit wiring, and is suitably employed in electronic devices employed in the high frequency region, and, in particular, in electronic devices that must be made smaller and lighter in weight.

    摘要翻译: 本发明涉及一种热固性低电介质树脂组合物,用于印刷布线的叠层体,电路用层压体等。 本发明的热固性低介电性树脂组合物含有特定的硅氧烷改性聚酰亚胺,具有2个以上烯丙基或甲基烯丙基的化合物和具有2个以上马来酰亚胺基的化合物。 该树脂组合物非常好地粘附在具有低介电常数和低介电损耗因子的金属上,并且在诸如冲压或切割的操作过程中表现出非常小的树脂散射。 通过对采用这种树脂组合物的电路使用层压板或层压板,可以更迅速地传播电信号,从而能够以更快的速度处理信号。 此外,本发明可以应用于形成小型化的电路布线,并且适用于在高频区域中使用的电子设备中,特别是在必须制造得更小更轻的电子设备中。

    Method And Structure For Compound Semiconductor Contact
    9.
    发明申请
    Method And Structure For Compound Semiconductor Contact 有权
    化合物半导体接触的方法与结构

    公开(公告)号:US20120261718A1

    公开(公告)日:2012-10-18

    申请号:US13085511

    申请日:2011-04-13

    IPC分类号: H01L29/78 H01L21/336

    摘要: The present disclosure provides a buried channel semiconductor structure in which a crystallographic wet etch is used to tailor the profile of etched regions formed into a multilayered substrate which includes a compound semiconductor layer located atop a buried semiconductor channel material layer. The use of crystallographic wet etching on a compound semiconductor allows one to tailor the shape of a source recess region and a drain recess region formed into a multilayered substrate. This allows for the control of gate overlap/underlap. Also, the use of crystallographic wet etching on a compound semiconductor allows independent control of the length of an underlying buried semiconductor channel region.

    摘要翻译: 本公开提供了掩埋沟道半导体结构,其中使用结晶湿蚀刻来定制形成多层衬底的蚀刻区域的轮廓,其包括位于掩埋半导体沟道材料层顶部的化合物半导体层。 在化合物半导体上使用结晶湿式蚀刻可以使形成多层基板的源极凹部区域和漏极凹陷区域的形状成为可能。 这允许控制栅极重叠/欠压。 此外,在化合物半导体上使用晶体湿式蚀刻可以独立控制下面的掩埋半导体沟道区的长度。