公开(公告)号：US07741679B2

公开(公告)日：2010-06-22

申请号：US11866693

申请日：2007-10-03

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L23/62

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US20100029321A1

公开(公告)日：2010-02-04

申请号：US12504816

申请日：2009-07-17

申请人： Shoichi Miyamoto

发明人： Shoichi Miyamoto

IPC分类号： H04W52/04 ,  H04B7/005

CPC分类号： H04W52/365 ,  H04W52/282 ,  H04W52/362 ,  H04W52/44

摘要： A mobile station device includes a receiving section configured to receive a control signal used for changing a value of the transmission power of the mobile station device from a base station, and a control section configured to change, if the transmission power value of the mobile station device is more than a certain threshold value when the control signal has been received, the transmission power value by setting an extent to which the transmission power value is to be changed as a certain extent of change, and, if the transmission power value of the radio mobile station device is less than the certain threshold value when the receiving section received, change the transmission power value by making the extent of change of the transmission power value smaller than the certain extent of change.

摘要翻译： 移动站装置包括：接收部，被配置为从基站接收用于改变移动台装置的发送功率的值的控制信号;以及控制部，其被配置为如果所述移动台的发送功率值 当已经接收到控制信号时，设备大于某个阈值，通过设定发送功率值将在一定程度上改变的程度来设置发送功率值，并且如果发送功率值为 当接收部分接收时，无线电移动台装置小于某个阈值，通过使传输功率值的变化程度小于一定的变化范围来改变发射功率值。

公开(公告)号：US20080315313A1

公开(公告)日：2008-12-25

申请号：US11866693

申请日：2007-10-03

申请人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US07061965B2

公开(公告)日：2006-06-13

申请号：US09999388

申请日：2001-10-31

申请人： Mayumi Kodani ,  Shoichi Miyamoto ,  Ayanori Matsuda ,  Takuya Mori

发明人： Mayumi Kodani ,  Shoichi Miyamoto ,  Ayanori Matsuda ,  Takuya Mori

IPC分类号： H04B1/69

CPC分类号： H04J13/18 ,  H04B2201/70703 ,  H04J13/0048

摘要： A Walsh code assigning apparatus includes a retaining unit retaining assignment order information about an order of assignment of the plural Walsh codes such that one Walsh code having a smaller bit length becomes unable to he orthogonally separated as being precedent over another Walsh code having a larger bit length and a controller including a retrieving unit retrieving an idle Walsh code having an assignment request bit length in accordance with the assignment order information retained in the retaining unit, and assigning unit assigning the idle Walsh code, which has been obtained by the retrieving unit, to the spreading code of a last-named communication channel for which the assignment request is issued.

摘要翻译： 沃尔什码分配装置包括保持单元，其保留关于多个沃尔什码的分配顺序的分配顺序信息，使得具有较小比特长度的一个沃尔什码不能正确地与另一个具有较大比特的沃尔什码进行正交分离 长度的控制器和包括检索单元的控制器，所述检索单元根据保留在保留单元中的分配顺序信息来检索具有分配请求位长度的空闲沃尔什码，以及分配单元，其分配由检索单元获得的空闲沃尔什码， 涉及发布分配请求的最后命名的通信信道的扩展码。

公开(公告)号：US20060086934A1

公开(公告)日：2006-04-27

申请号：US11293171

申请日：2005-12-05

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L29/08 ,  H01L29/04 ,  H01L27/12 ,  H01L27/14

CPC分类号： H01L21/76297 ,  H01L21/26586 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

公开(公告)号：US06958266B2

公开(公告)日：2005-10-25

申请号：US10120485

申请日：2002-04-12

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

公开(公告)号：US06603174B2

公开(公告)日：2003-08-05

申请号：US09197705

申请日：1998-11-23

申请人： Shoichi Miyamoto ,  Yuuichi Hirano ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Yuuichi Hirano ,  Takashi Ipposhi

IPC分类号： H01L2701

CPC分类号： H01L29/66772 ,  H01L21/28123 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/42384

摘要： An SOI substrate (30) comprises a buried oxide film (2), an SOI layer (3) formed on a first region (51) of the surface (2S) of the buried oxide film, and a silicon oxide film (8) formed on a second region (52) of the surface (2S). Formed on the peripheral portion of the SOI layer (3) is a silicon oxide film (6), the side surface (6H) of which is integrally joined to the side surface (8H) of the silicon oxide film (8). The thickness of the peripheral portion of the SOI layer (3) decreases as closer to the end portion (3H) of the SOI layer (3), while the thickness of the silicon oxide film (6) formed on the peripheral portion of the SOI layer (3) increases as closer to the end portion (3H). A gate oxide film (9) is formed on a predetermined region of the surface of the SOI layer (3), and joined to the silicon oxide film (6) at its end portion. A gate electrode (10) is then formed on the surface of the gate oxide film (9) and on a portion where the silicon oxide film (6) is integrally joined to the gate oxide film (9). In this manner, an SOI/MOSFET is obtained with no parasitic element formed at the end portion of the SOI layer.

摘要翻译： SOI衬底（30）包括掩埋氧化膜（2），形成在掩埋氧化膜的表面（2S）的第一区域（51）上的SOI层（3）和形成的氧化硅膜（8） 在表面（2S）的第二区域（52）上。 在SOI层（3）的周边部分上形成氧化硅膜（6），其氧化硅膜（6）的一侧与表面（8H）形成一体。 SOI层（3）的周边部的厚度比SOI层（3）的端部（3H）更靠近，而在SOI的外周部形成的氧化硅膜（6）的厚度 层（3）越靠近端部（3H）越大。 栅极氧化膜（9）形成在SOI层（3）的表面的规定区域上，并在其端部与氧化硅膜（6）接合。 然后，在栅极氧化膜（9）的表面和氧化硅膜（6）与栅氧化膜（9）整体接合的部分上形成栅电极（10）。 以这种方式，在SOI层的端部没有形成寄生元件的SOI / MOSFET得到。

公开(公告)号：US06509583B1

公开(公告)日：2003-01-21

申请号：US09677848

申请日：2000-10-03

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L2904

CPC分类号： H01L21/76297 ,  H01L21/26586 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.