公开(公告)号：US08481379B2

公开(公告)日：2013-07-09

申请号：US13375976

申请日：2011-08-10

申请人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

发明人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L29/66795

摘要： An embodiment of the present invention discloses a method for manufacturing a FinFET, when a fin is formed, a dummy gate across the fin is formed on the fin, a source/drain opening is formed in both the cover layer and the first dielectric layer at both sides of the dummy gate, the source/drain opening is at both sides of the fin covered by the dummy gate and is an opening region surrounded by the cover layer and the first dielectric layer around it. In the formation of a source/drain region in the source/drain opening, stress is generated due to lattice mismatching, and applied to the channel due to the limitation by the source/drain opening in the first dielectric layer, thereby increasing the carrier mobility of the device, and improving the performance of the device.

摘要翻译： 本发明的一个实施例公开了一种制造FinFET的方法，在翅片形成时，在翅片上形成跨鳍片的虚拟栅极，在覆盖层和第一电介质层中形成源极/漏极开口 虚拟栅极的两侧，源极/漏极开口处于由虚拟栅极覆盖的鳍的两侧，并且是由覆盖层和围绕其的第一介电层包围的开口区域。 在源极/漏极开口中的源极/漏极区域的形成中，由于晶格失配而产生应力，并且由于第一介电层中的源极/漏极开口的限制而施加到沟道，从而增加载流子迁移率 的设备，并提高设备的性能。

公开(公告)号：US20130153913A1

公开(公告)日：2013-06-20

申请号：US13698276

申请日：2011-11-30

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L21/02 ,  H01L27/088

CPC分类号： H01L21/02107 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203

摘要： A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost.

摘要翻译： 在本发明中公开了晶体管，晶体管的制造方法以及包括该晶体管的半导体器件。 制造晶体管的方法可以包括：提供衬底并在衬底上形成第一绝缘层; 限定所述第一绝缘层上的第一器件区域; 在所述第一绝缘层上形成围绕所述第一器件区域的间隔物; 在所述第一绝缘层上限定第二器件区域，其中所述第二器件区域通过所述间隔物与所述第一器件区域隔离; 以及分别在第一和第二器件区域中形成晶体管结构。 本发明的晶体管的制造方法大大降低了隔离所需的空间，显着地降低了工艺的复杂性，大大降低了制造成本。

公开(公告)号：US20120309139A1

公开(公告)日：2012-12-06

申请号：US13375976

申请日：2011-08-10

申请人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

发明人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/66795

摘要： An embodiment of the present invention discloses a method for manufacturing a FinFET, when a fin is formed, a dummy gate across the fin is formed on the fin, a source/drain opening is formed in both the cover layer and the first dielectric layer at both sides of the dummy gate, the source/drain opening is at both sides of the fin covered by the dummy gate and is an opening region surrounded by the cover layer and the first dielectric layer around it. In the formation of a source/drain region in the source/drain opening, stress is generated due to lattice mismatching, and applied to the channel due to the limitation by the source/drain opening in the first dielectric layer, thereby increasing the carrier mobility of the device, and improving the performance of the device.

摘要翻译： 本发明的一个实施例公开了一种制造FinFET的方法，在翅片形成时，在翅片上形成跨鳍片的虚拟栅极，在覆盖层和第一电介质层中形成源极/漏极开口 虚拟栅极的两侧，源极/漏极开口处于由虚拟栅极覆盖的鳍的两侧，并且是由覆盖层和围绕其的第一介电层包围的开口区域。 在源极/漏极开口中的源极/漏极区域的形成中，由于晶格失配而产生应力，并且由于第一介电层中的源极/漏极开口的限制而施加到沟道，从而增加载流子迁移率 的设备，并提高设备的性能。

公开(公告)号：US20120126244A1

公开(公告)日：2012-05-24

申请号：US13119004

申请日：2011-01-27

申请人： Huicai Zhong ,  Haizhou Yin ,  Qingqing Liang ,  Huilong Zhu

发明人： Huicai Zhong ,  Haizhou Yin ,  Qingqing Liang ,  Huilong Zhu

IPC分类号： H01L29/12 ,  H01L29/16 ,  H01L21/761 ,  H01L27/04 ,  H01L21/762

CPC分类号： H01L29/7846 ,  H01L21/76224

摘要： The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.

摘要翻译： 本发明提供一种STI结构及其制造方法。 STI包括半导体衬底; 形成在所述半导体衬底的上表面上并填充有外延层的第一沟槽，其中所述外延层的上表面高于所述半导体衬底的所述外表面; 以及形成在所述外延层上并且填充有第一介电层的第二沟槽，其中所述第一电介质层的上表面与所述外延层的上表面齐平，并且所述第二沟槽的宽度小于所述第一沟槽的宽度 。 本发明减少了对于半导体器件性能的影响。

公开(公告)号：US20120097923A1

公开(公告)日：2012-04-26

申请号：US13140141

申请日：2011-02-24

申请人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Xinyu Liu ,  Huilong Zhu

发明人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Xinyu Liu ,  Huilong Zhu

IPC分类号： H01L29/786 ,  H01L29/165 ,  H01L21/336 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L29/778 ,  H01L29/1606 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78684

摘要： The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.

摘要翻译： 本发明提供了一种石墨烯器件结构及其制造方法，该器件结构包括石墨烯层; 与石墨烯层接触的栅极区域; 半导体掺杂区域形成在栅极区域的两个相对侧并与石墨烯层接触，其中半导体掺杂区域与栅极区域隔离; 在栅极区域上形成的触点和形成在半导体掺杂区域上的触点。 通过半导体掺杂区域增加石墨烯器件的开关比，而不增加石墨烯材料的带隙，即不影响材料的迁移率或器件的速度，从而增加石墨烯材料的适用性 在CMOS设备中。

公开(公告)号：US20150311319A1

公开(公告)日：2015-10-29

申请号：US14406904

申请日：2012-08-17

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.

摘要翻译： 本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

公开(公告)号：US08895403B2

公开(公告)日：2014-11-25

申请号：US13698276

申请日：2011-11-30

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/02107 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203

摘要： A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost.

摘要翻译： 在本发明中公开了晶体管，晶体管的制造方法以及包括该晶体管的半导体器件。 制造晶体管的方法可以包括：提供衬底并在衬底上形成第一绝缘层; 限定所述第一绝缘层上的第一器件区域; 在所述第一绝缘层上形成围绕所述第一器件区域的间隔物; 在所述第一绝缘层上限定第二器件区域，其中所述第二器件区域通过所述间隔物与所述第一器件区域隔离; 以及分别在第一和第二器件区域中形成晶体管结构。 本发明的晶体管的制造方法大大降低了隔离所需的空间，显着地降低了工艺的复杂性，大大降低了制造成本。

公开(公告)号：US08846488B2

公开(公告)日：2014-09-30

申请号：US13578598

申请日：2011-11-30

申请人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L21/76 ,  H01L29/78 ,  H01L21/762 ,  H01L21/265

CPC分类号： H01L21/76224 ,  H01L21/26506 ,  H01L29/7842 ,  H01L29/7847

摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分 引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。 根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

公开(公告)号：US20130221329A1

公开(公告)日：2013-08-29

申请号：US13582431

申请日：2012-03-29

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Zhi Jin ,  Xinyu Liu ,  Tianchun Ye

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Zhi Jin ,  Xinyu Liu ,  Tianchun Ye

IPC分类号： H01L29/66

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/778

摘要： An embodiment of the invention discloses a graphene device comprising a plurality of graphene channels and a gate, wherein one end of all the graphene channels is connected to one terminal, all the graphene channels are in contact with and electrically connected with the gate, and the angles between the graphene channels and the gate are mutually different. Due to a different incident wave angle for a different graphene channel, each of the graphene channels has a different tunneling probability, each of the graphene channels has a different conduction condition, and the graphene device may be used as a device such as a multiplexer or a demultiplexer, etc.

摘要翻译： 本发明的实施例公开了一种石墨烯装置，其包括多个石墨烯通道和一个浇口，其中所有石墨烯通道的一端连接到一个端子，所有的石墨烯通道与浇口接触并与门电连接， 石墨烯通道和栅极之间的角度是相互不同的。 由于不同石墨烯通道的不同的入射波角，每个石墨烯通道具有不同的隧道概率，每个石墨烯通道具有不同的导电条件，并且石墨烯装置可以用作诸如多路复用器或 解复用器等

公开(公告)号：US08492210B2

公开(公告)日：2013-07-23

申请号：US13144906

申请日：2011-02-25

申请人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

发明人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

IPC分类号： H01L21/84

CPC分类号： H01L29/78648 ,  H01L21/8213 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66628

摘要： The invention relates to a transistor, a semiconductor device comprising the transistor and manufacturing methods for the transistor and the semiconductor device. The transistor according to the invention comprises: a substrate comprising at least a base layer, a first semiconductor layer, an insulating layer and a second semiconductor layer stacked sequentially; a gate stack formed on the second semiconductor layer; a source region and a drain region located on both sides of the gate stack respectively; a back gate comprising a back gate dielectric and a back gate electrode formed by the insulating layer and the first semiconductor layer, respectively; and a back gate contact formed on a portion of the back gate electrode. The back gate contact comprises an epitaxial part raised from the surface of the back gate electrode, and each of the source region and the drain region comprises an epitaxial part raised from the surface of the second semiconductor layer. As compared to a conventional transistor, the manufacturing process of the transistor of the invention is simplified and the cost of manufacture is reduced.

摘要翻译： 本发明涉及晶体管，包括晶体管的半导体器件和用于晶体管和半导体器件的制造方法。 根据本发明的晶体管包括：至少包括基层，第一半导体层，绝缘层和顺序层叠的第二半导体层的基板; 形成在所述第二半导体层上的栅叠层; 分别位于栅极堆叠的两侧的源极区域和漏极区域; 包括分别由所述绝缘层和所述第一半导体层形成的背栅电介质和背栅电极的背栅; 以及形成在背栅电极的一部分上的背栅极接触。 背栅极触点包括从背栅电极的表面凸起的外延部分，源区和漏区中的每一个包括从第二半导体层的表面凸出的外延部。 与常规晶体管相比，本发明的晶体管的制造工艺简化，制造成本降低。