公开(公告)号：US08637935B2

公开(公告)日：2014-01-28

申请号：US13266555

申请日：2011-04-19

申请人： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Huilong Zhu

发明人： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Huilong Zhu

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L29/66636 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848

摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.

摘要翻译： 一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。 还提供了半导体器件。 可以减小隔离区域的面积。

公开(公告)号：US20120126244A1

公开(公告)日：2012-05-24

申请号：US13119004

申请日：2011-01-27

申请人： Huicai Zhong ,  Haizhou Yin ,  Qingqing Liang ,  Huilong Zhu

发明人： Huicai Zhong ,  Haizhou Yin ,  Qingqing Liang ,  Huilong Zhu

IPC分类号： H01L29/12 ,  H01L29/16 ,  H01L21/761 ,  H01L27/04 ,  H01L21/762

CPC分类号： H01L29/7846 ,  H01L21/76224

摘要： The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.

摘要翻译： 本发明提供一种STI结构及其制造方法。 STI包括半导体衬底; 形成在所述半导体衬底的上表面上并填充有外延层的第一沟槽，其中所述外延层的上表面高于所述半导体衬底的所述外表面; 以及形成在所述外延层上并且填充有第一介电层的第二沟槽，其中所述第一电介质层的上表面与所述外延层的上表面齐平，并且所述第二沟槽的宽度小于所述第一沟槽的宽度 。 本发明减少了对于半导体器件性能的影响。

公开(公告)号：US20120187496A1

公开(公告)日：2012-07-26

申请号：US13266555

申请日：2011-04-19

申请人： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Huilong Zhu

发明人： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Huilong Zhu

IPC分类号： H01L27/088 ,  H01L21/302

CPC分类号： H01L29/66636 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848

摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.

摘要翻译： 一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。 还提供了半导体器件。 可以减小隔离区域的面积。

公开(公告)号：US08269307B2

公开(公告)日：2012-09-18

申请号：US13119004

申请日：2011-01-27

申请人： Huicai Zhong ,  Haizhou Yin ,  Qingqing Liang ,  Huilong Zhu

发明人： Huicai Zhong ,  Haizhou Yin ,  Qingqing Liang ,  Huilong Zhu

IPC分类号： H01L29/15

CPC分类号： H01L29/7846 ,  H01L21/76224

摘要： The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.

摘要翻译： 本发明提供一种STI结构及其制造方法。 STI包括半导体衬底; 形成在所述半导体衬底的上表面上并填充有外延层的第一沟槽，其中所述外延层的上表面高于所述半导体衬底的所述外表面; 以及形成在所述外延层上并且填充有第一介电层的第二沟槽，其中所述第一电介质层的上表面与所述外延层的上表面齐平，并且所述第二沟槽的宽度小于所述第一沟槽的宽度 。 本发明减少了对于半导体器件性能的影响。

公开(公告)号：US20130200456A1

公开(公告)日：2013-08-08

申请号：US13696995

申请日：2011-11-29

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Huicai Zhong

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Huicai Zhong

IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L21/762

CPC分类号： H01L27/12 ,  H01L21/743 ,  H01L21/762 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.

摘要翻译： 本发明涉及半导体衬底，具有半导体衬底的集成电路及其制造方法。 根据本发明的包括具有背栅的晶体管的集成电路中使用的半导体衬底包括：半导体基底层; 半导体基底层上的第一绝缘材料层; 第一绝缘材料层上的第一导电材料层; 在所述第一导电材料层上的第二绝缘材料层; 在所述第二绝缘材料层上的第二导电材料层; 第二导电材料层上的绝缘掩埋层; 以及在所述绝缘埋层上的半导体层，其中，在所述第一导电材料层和所述第二导电材料层之间设置有至少一个第一导电通孔，以穿透所述第二绝缘材料层，以将所述第一导电材料层与 第二导电材料层，每个第一导电通孔的位置由要形成第一组晶体管中的对应一个的区域限定。

公开(公告)号：US08957481B2

公开(公告)日：2015-02-17

申请号：US13379407

申请日：2011-05-11

申请人： Huilong Zhu ,  Huicai Zhong ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Huicai Zhong ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L21/70 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/308 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L21/3086 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/66636 ,  H01L29/7848

摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. Compared with conventional approaches to form contacts, the present disclosure reduces contact resistance and avoids a short circuit between a gate and contact plugs, while simplifying manufacturing process, increasing integration density, and lowering manufacture cost. According to the manufacturing method of the present disclosure, second shallow trench isolations are formed with an upper surface higher than an upper surface of the source/drain regions. Regions defined by sidewall spacers of the gate, sidewall spacers of the second shallow trench isolations, and the upper surface of the source/drain regions are formed as contact holes. The contacts are formed by filling the contact holes with a conductive material. The method omits the steps of etching for providing the contact holes, which lowers manufacture cost. By forming the contacts self-aligned with the gate, the method avoids misalignment and improves performance of the device while reducing a footprint of the device and lowering manufacture cost of the device.

摘要翻译： 本申请公开了一种半导体结构及其制造方法。 与传统的形成触点的方法相比，本公开减少了接触电阻，并且避免了栅极和接触插塞之间的短路，同时简化了制造工艺，增加了集成密度并降低了制造成本。 根据本公开的制造方法，形成第二浅沟槽隔离件，其上表面高于源极/漏极区域的上表面。 由栅极的侧壁间隔物，第二浅沟槽隔离件的侧壁间隔件和源极/漏极区域的上表面限定的区域形成为接触孔。 通过用导电材料填充接触孔来形成触点。 该方法省略了用于提供接触孔的蚀刻步骤，这降低了制造成本。 通过形成与栅极自对准的触点，该方法避免了未对准并且提高了器件的性能，同时减少了器件的占地面积并降低了器件的制造成本。

公开(公告)号：US08829621B2

公开(公告)日：2014-09-09

申请号：US13696995

申请日：2011-11-29

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Huicai Zhong

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Huicai Zhong

IPC分类号： H01L21/70 ,  H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L21/74 ,  H01L21/762 ,  H01L29/786

CPC分类号： H01L27/12 ,  H01L21/743 ,  H01L21/762 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.

摘要翻译： 本发明涉及半导体衬底，具有半导体衬底的集成电路及其制造方法。 根据本发明的包括具有背栅的晶体管的集成电路中使用的半导体衬底包括：半导体基底层; 半导体基底层上的第一绝缘材料层; 第一绝缘材料层上的第一导电材料层; 在所述第一导电材料层上的第二绝缘材料层; 在所述第二绝缘材料层上的第二导电材料层; 第二导电材料层上的绝缘掩埋层; 以及在所述绝缘埋层上的半导体层，其中，在所述第一导电材料层和所述第二导电材料层之间设置有至少一个第一导电通孔，以穿透所述第二绝缘材料层，以将所述第一导电材料层与 第二导电材料层，每个第一导电通孔的位置由要形成第一组晶体管中的对应一个的区域限定。

公开(公告)号：US08633522B2

公开(公告)日：2014-01-21

申请号：US13062733

申请日：2010-09-20

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Huicai Zhong

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Huicai Zhong

IPC分类号： H01L29/78

CPC分类号： H01L29/7834 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor structure and a method for fabricating the same. A semiconductor structure includes a semiconductor substrate; a channel region formed in the semiconductor substrate; a gate including a dielectric layer and a conductive layer and formed above the channel region; source and drain regions formed at opposing sides of the gate; first shallow trench isolations embedded into the semiconductor substrate and having a length direction parallel to the length direction of the gate; and second shallow trench isolations, each of which abuts the outer sidewall of the source or the drain region and abuts the first shallow trench isolations, in which the source and drain regions include first seed crystal layers abutting the second shallow trench isolations, and the top surfaces of the second shallow trench isolations are higher than or as high as the top surfaces of the source and drain regions.

摘要翻译： 半导体结构及其制造方法。 半导体结构包括半导体衬底; 形成在所述半导体衬底中的沟道区; 包括电介质层和导电层并形成在沟道区上方的栅极; 源极和漏极区域形成在栅极的相对侧; 第一浅沟槽隔离物嵌入半导体衬底并具有平行于栅极长度方向的长度方向; 以及第二浅沟槽隔离件，每个隔离件邻接源极或漏极区域的外侧壁并邻接第一浅沟槽隔离物，其中源极和漏极区域包括邻接第二浅沟槽隔离物的第一晶种层和顶部 第二浅沟槽隔离物的表面高于或高于源区和漏区的顶表面。

公开(公告)号：US20120273901A1

公开(公告)日：2012-11-01

申请号：US13063733

申请日：2010-09-27

申请人： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/49 ,  H01L29/66583 ,  H01L29/7833

摘要： The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, when a gate is formed via a replacement gate process, a portion of a work function metal layer and a portion of a first metal layer are removed after the work function metal layer and the first metal layer are formed, and then the removed portions are replaced with a second metal layer. A device having such a gate structure greatly reduces the resistivity of the whole gate, due to a portion of the work function metal layer with a high resistivity being removed and the removed portion being filled with the second metal layer with a low resistivity, thereby AC performances of the device are improved.

摘要翻译： 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 根据本发明，当通过替换栅极工艺形成栅极时，在形成功函数金属层和第一金属层之后，去除功函数金属层的一部分和第一金属层的一部分，以及 然后用第二金属层代替去除的部分。 具有这种栅极结构的器件大大降低了整个栅极的电阻率，这是由于去除具有高电阻率的功函数金属层的一部分并且被去除的部分被低电阻率的第二金属层填充，由此AC 改善了设备的性能。

公开(公告)号：US20120168881A1

公开(公告)日：2012-07-05

申请号：US13142591

申请日：2011-01-27

申请人： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/7846 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 制造半导体器件的方法包括：提供其上形成有栅极叠层结构并具有{100}晶体指数的硅衬底; 形成层叠所述硅衬底的顶表面的层间电介质层; 在所述层间介质层和/或所述栅堆叠结构中形成第一沟槽，所述第一沟槽具有沿着晶体方向并且垂直于所述栅堆叠结构的延伸方向; 以及用第一介电层填充所述第一沟槽，其中所述第一介电层是拉伸应力介电层。 本发明通过使用简单的工艺在沟道区域的横向上引入拉伸应力，这提高了半导体器件的响应速度和性能。