公开(公告)号：US11562963B2

公开(公告)日：2023-01-24

申请号：US16987440

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Chin Lee Kuan ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Sameer Shekhar ,  Amit Jain

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.

公开(公告)号：US11557552B2

公开(公告)日：2023-01-17

申请号：US16818603

申请日：2020-03-13

Applicant: Intel Corporation

Inventor： Chin Lee Kuan ,  Jackson Chung Peng Kong ,  Bok Eng Cheah

IPC: H01L23/66 ,  H01L23/498

Abstract: A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.

公开(公告)号：US11342852B2

公开(公告)日：2022-05-24

申请号：US15631996

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： Sameer Shekhar ,  Amit K. Jain ,  Alexander Waizman ,  Michael Zelikson ,  Chin Lee Kuan

IPC: H02M3/158 ,  H02M3/335 ,  G05F1/46 ,  H02M1/36 ,  H02M3/24

Abstract: An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.

公开(公告)号：US20210335712A1

公开(公告)日：2021-10-28

申请号：US17371293

申请日：2021-07-09

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Chin Lee Kuan ,  Kevin Joseph Doran ,  Dong-Ho Han

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

公开(公告)号：US20180145042A1

公开(公告)日：2018-05-24

申请号：US15359926

申请日：2016-11-23

Applicant: INTEL CORPORATION

Inventor： Min Suet Lim ,  Chin Lee Kuan ,  Eng Huat Goh ,  Khang Choong Yong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Howe Yin Loo

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816

Abstract: A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.