公开(公告)号：US12250800B2

公开(公告)日：2025-03-11

申请号：US17482244

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Yew San Lim ,  Jeff Ku ,  Boon Ping Koh ,  Min Suet Lim ,  Tin Poay Chuah

IPC: H05K9/00 ,  H05K1/02 ,  H05K7/20

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a radiation shield that includes a zipper. The radiation shield can include a wall that extends from a support structure of the electronic device, a first portion that is coupled to a cold plate over a radiation source, a second portion that is coupled to the wall, and a zipper that can zip the first portion to the second portion together and can unzip to separate the first portion from the second portion.

公开(公告)号：US20250024643A1

公开(公告)日：2025-01-16

申请号：US18897895

申请日：2024-09-26

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Smit Kapila ,  Shantanu Kulkarni ,  Min Suet Lim ,  Surya Pratap Mishra

IPC: H05K7/20

Abstract: A thermal ground plane (TGP), including: a vapor chamber containing an ionized fluid; a reservoir fluidly connected with the vapor chamber, configured to store excess ionized fluid; and an electromagnetic source configured to dynamically direct a variable amount of the excess ionized fluid from the reservoir to the vapor chamber based on a thermal resistance of the ionized fluid in the vapor chamber or a temperature of the TGP at a location proximate to a heat source.

公开(公告)号：US20250008661A1

公开(公告)日：2025-01-02

申请号：US18343993

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Arturo Navarro Alvarez ,  Jeff Ku ,  Luis Carlos Sanchez Herrera ,  Min Suet Lim ,  Pin Wang ,  Tongyan Zhai ,  Raghavendra Ramesh Rao

IPC: H05K1/18

Abstract: Deflection spring compression mounting is disclosed. A disclosed example deflection spring for an electronics package includes first and second end portions having first and second locking interfaces, respectively, to at least partially constrain the first and second end portions relative to a support, a curved portion, and a medial portion having a third locking interface to fix the medial portion relative to the support, wherein fixing the medial portion relative to the support causes the curved portion to contact and press against the electronics package.

公开(公告)号：US12146476B2

公开(公告)日：2024-11-19

申请号：US17561605

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Mark J. Gallina ,  Min Suet Lim ,  Jianfang Zhu

IPC: H05K7/20 ,  F03G7/06

Abstract: Particular embodiments described herein provide for a flexible vapor chamber with shape memory material for an electronic device. In an example, the electronic device can include a flexible vapor chamber and shape memory material coupled to the shape memory material. When the shape memory material is activated, the shape memory material moves a portion of the flexible vapor chamber to a position that helps with heat dissipation of heat collected by the flexible vapor chamber.

公开(公告)号：US20240312869A1

公开(公告)日：2024-09-19

申请号：US18183505

申请日：2023-03-14

Applicant: Intel Corporation

Inventor： Tongyan Zhai ,  Telesphor Kamgaing ,  Min Suet Lim

IPC: H01L23/473 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L23/473 ,  H01L23/528 ,  H01L24/32 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. A microfluidic cooling layer is formed near a top or front the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices.

公开(公告)号：US12066833B2

公开(公告)日：2024-08-20

申请号：US17322056

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Maruti Gupta Hyde ,  Min Suet Lim ,  Van Le ,  Hebatallah Saadeldeen

IPC: G05D1/00 ,  B60W30/00 ,  G08G1/01 ,  H04W4/029 ,  H04W4/38 ,  H04W4/44

CPC classification number: G05D1/0276 ,  B60W30/00 ,  G05D1/0231 ,  G08G1/0116 ,  H04W4/029 ,  H04W4/38 ,  H04W4/44

Abstract: The present disclosure may be directed to a computer-assisted or autonomous driving (CA/AD) vehicle that receives a plurality of indications of a condition of one or more features of a plurality of locations of a roadway, respectively, encoded in a plurality of navigation signals broadcast by a plurality of transmitters as the CA/AD vehicle drives past the locations enroute to a destination. The CA/AD vehicle may then determine, based in part on the received indications, driving adjustments to be made and send indications of the driving adjustments to a driving control unit of the CA/AD vehicle.

公开(公告)号：US20240244772A1

公开(公告)日：2024-07-18

申请号：US18619554

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Smit Kapila ,  Jeff Ku ,  Min Suet Lim ,  Sarma Vmk Vedhanabhatla

IPC: H05K5/02

CPC classification number: H05K5/0213

Abstract: Techniques are described to dynamically adjust the open air ratio (OAR) while ensuring compliance with regulatory requirements. An adjustable thermal vent assembly is described that dynamically adjusts the OAR for inlet/outlet vents depending on the current use case. The adjustable thermal vent assembly functions to increase the grating spacing only when a triggering condition is met that ensures that a corresponding thermal vent location is inaccessible. Such temporarily inaccessible regions may include the bottom cover of an electronic device when positioned on the surface of an object, for thermal intake vents, or the rear portion of an electronic device when the display cover exceeds a predetermined angle, for thermal exhaust vents.

公开(公告)号：US11798894B2

公开(公告)日：2023-10-24

申请号：US16451557

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Kooi Chi Ooi ,  Min Suet Lim

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2924/3025

Abstract: The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 μm pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.

公开(公告)号：US11699664B2

公开(公告)日：2023-07-11

申请号：US17089756

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Tin Poay Chuah ,  Yew San Lim ,  Min Suet Lim

IPC: H01L23/552 ,  H05K3/28 ,  H05K1/02

CPC classification number: H01L23/552 ,  H05K1/0209 ,  H05K3/284

Abstract: According to the various aspects, the present device includes a printed circuit board having a top surface and a bottom surface, with a plurality of semiconductor devices coupled to the top surface and a flexible electromagnetic shield wrap conformally positioned over and between the plurality of semiconductor devices and the top surface of the printed circuit board. The flexible electromagnetic shield wrap is conformally positioned by applying a vacuum and is removable after the vacuum seal is broken.

公开(公告)号：US20220300692A1

公开(公告)日：2022-09-22

申请号：US17835323

申请日：2022-06-08

Applicant: Intel Corporation

Inventor： Jin Yan ,  Adam Norman ,  Min Suet Lim ,  Mackenzie Norman ,  Hong Cheah Ho ,  Jianfang Zhu ,  Miaomiao Ma

IPC: G06F30/392 ,  G06F30/398

Abstract: Systems, apparatuses and methods may provide for technology that identifies a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components, conducts one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components, and conducts, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios.