公开(公告)号：US20190182730A1

公开(公告)日：2019-06-13

申请号：US16274865

申请日：2019-02-13

Applicant: Intel Corporation

Inventor： Shu-Ping Yeh ,  Jingwen Bai ,  Feng Xue ,  Candy Yiu

IPC: H04W36/08 ,  H04W36/24 ,  H04W24/10 ,  H04W76/27 ,  H04L12/26

Abstract: To configure a UE for handover between a source evolved Node-B (eNB) and a target eNB using aerial communications in a cellular network, the UE processing circuitry is to decode measurement configuration information from the source eNB. The measurement configuration information includes a plurality of height thresholds associated with aerial height of the UE. A measurement report is encoded for transmission to the source eNB. The measurement report includes the aerial height of the UE and the measurement report generation triggered based on one or more triggering events associated with the plurality of height thresholds. RRC signaling from the source eNB is decoded, the RRC signaling including a handover command. The handover command is based on a handover decision by the source eNB using the measurement report. A handover from the source eNB to the target eNB is performed based on the handover command.

公开(公告)号：US10193683B2

公开(公告)日：2019-01-29

申请号：US15214531

申请日：2016-07-20

Applicant: Intel Corporation

Inventor： Chia-Hsiang Chen ,  Ching-En Lee ,  Feng Xue ,  Shu-Ping Yeh

IPC: H04L5/14 ,  H04B1/44 ,  H04B15/00 ,  H04B1/525

Abstract: A communication circuit arrangement includes a signal path circuit configured to separately apply a kernel dimension filter and a delay tap dimension filter to an input signal for an amplifier to obtain an estimated interference signal, a cancelation circuit configured to subtract the estimated interference signal from a received signal to obtain a clean signal, and a filter update circuit configured to alternate between updating the kernel dimension filter and the delay tap dimension filter using the clean signal.

公开(公告)号：US09935615B2

公开(公告)日：2018-04-03

申请号：US14861421

申请日：2015-09-22

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Ching-En Lee ,  Feng Xue ,  Anuja S. Vaidya ,  Eduardo X. Alban ,  Albert Oskar Filip Andersson ,  Chia-Hsiang Chen ,  Shu-Ping Yeh

IPC: G06F17/10 ,  H03H21/00 ,  G06F17/16 ,  G06F9/38 ,  H04B1/525

CPC classification number: H03H21/0012 ,  G06F9/3877 ,  G06F17/16 ,  H03H2021/0049 ,  H03H2021/0094 ,  H03H2218/06 ,  H04B1/525

Abstract: An adaptation hardware accelerator comprises a calculation unit to receive inputs at predefined time interval(s) that correspond to a calculation iteration, the inputs associated with adaptive filters having taps, and determine correlation and cross-correlation data based thereon for a given iteration. The correlation data comprises a correlation matrix. Determining the matrix comprises determining submatrices in an upper triangular portion and a diagonal portion of the matrix. The accelerator comprises an adaptation core unit to determine adaptive weights associated with the adaptive filters, respectively, based on an adaptive algorithm, utilizing the correlation and cross correlation data. The accelerator unit comprises a convergence detector unit to determine a convergence parameter; and a controller to generate an iteration signal for each time interval based on the parameter. The iteration signal communicates to continue or conclude; the conclusion indicates determination of a final value of adaptive weights by the core unit.

公开(公告)号：US09866264B2

公开(公告)日：2018-01-09

申请号：US15393309

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Feng Xue ,  Yang-Seok Choi ,  Shu-Ping Yeh ,  Shilpa Talwar ,  Roya Doostnejad

IPC: H04B1/44 ,  H04B1/525

CPC classification number: H04B1/44 ,  H04B1/525 ,  H04B17/391

Abstract: A method of processing signals may include identifying a plurality of critical elements of a parameter vector based on one or more predefined criteria, wherein the parameter vector represents a relationship between the input signal vector and the output signal vector; identifying a reduced parameter update vector having a plurality of elements, wherein the elements are selected according to a criterion related to the relationship between the input signal vector and the output signal vector; updating the plurality of critical elements of the parameter vector using the reduced parameter update vector to generate an updated parameter vector, wherein the reduced parameter update vector has less elements than the parameter vector; and processing one or more signals associated with the input signal vector using the updated parameter vector.

公开(公告)号：US09667292B2

公开(公告)日：2017-05-30

申请号：US14751236

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Feng Xue ,  Yang-Seok Choi ,  Shu-Ping Yeh ,  Shilpa Talwar

IPC: H04B1/40 ,  H04B1/12

CPC classification number: H04B1/123 ,  H04B1/40

Abstract: A data processing system may include a transmit circuit configured to transmit a first signal sequence comprising one or more signals, a receive circuit configured to transmit a second signal sequence comprising one or more additional signals, wherein one or more signals of the second signal sequence comprise an interference component related to the first signal sequence, and a processing circuit. The processing circuit may be configured to generate a kernel set comprising one or more kernels based on the first signal sequence, wherein a first kernel of the kernel set comprises: a first complex exponential component of the first kernel based on the phase of a first signal of the first signal sequence, and a second complex exponential component of the first kernel based on the amplitude of the first signal of the first signal sequence, and apply the kernel set to generate a solution to a linear system, wherein the solution to the linear system represents a substantially linear relationship between the kernel set and the signal component of the second signal sequence arising from the first signal sequence.

公开(公告)号：US20160380661A1

公开(公告)日：2016-12-29

申请号：US14751236

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Feng Xue ,  Yang-Seok Choi ,  Shu-Ping Yeh ,  Shilpa Talwar

IPC: H04B1/12 ,  H04B1/40

CPC classification number: H04B1/123 ,  H04B1/40

Abstract: A data processing system may include a transmit circuit configured to transmit a first signal sequence comprising one or more signals, a receive circuit configured to transmit a second signal sequence comprising one or more additional signals, wherein one or more signals of the second signal sequence comprise an interference component related to the first signal sequence, and a processing circuit. The processing circuit may be configured to generate a kernel set comprising one or more kernels based on the first signal sequence, wherein a first kernel of the kernel set comprises: a first complex exponential component of the first kernel based on the phase of a first signal of the first signal sequence, and a second complex exponential component of the first kernel based on the amplitude of the first signal of the first signal sequence, and apply the kernel set to generate a solution to a linear system, wherein the solution to the linear system represents a substantially linear relationship between the kernel set and the signal component of the second signal sequence arising from the first signal sequence.

Abstract translation: 数据处理系统可以包括被配置为发送包括一个或多个信号的第一信号序列的发射电路，被配置为发送包括一个或多个附加信号的第二信号序列的接收电路，其中第二信号序列的一个或多个信号包括 与第一信号序列相关的干扰分量，以及处理电路。 处理电路可以被配置为基于第一信号序列来生成包括一个或多个内核的内核集，其中该内核集合的第一内核包括：基于第一信号的相位的第一内核的第一复指数分量 的第一信号序列的第一复数指数分量，以及基于第一信号序列的第一信号的振幅的第一复数指数分量，并且将该核集合应用于生成线性系统的解，其中， 系统表示核心组与第一信号序列产生的第二信号序列的信号分量之间的基本线性关系。

公开(公告)号：US20160380653A1

公开(公告)日：2016-12-29

申请号：US14749766

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Ching-En Lee ,  Shu-Ping Yeh ,  Feng Xue ,  Anuja Surendra Vaidya

IPC: H04B1/04 ,  H04L5/14 ,  H04B1/12

CPC classification number: H04B1/0475 ,  H04B1/12 ,  H04B1/525 ,  H04L5/14

Abstract: A polynomial kernel generator is configured to mitigate nonlinearity in a receiver path from a transmitter path comprising a nonlinear component in a communication device or system. The polynomial kernel generator operates to generate polynomial kernels that can be utilized to model the nonlinearity as a function of a piecewise polynomial approximation applied to a nonlinear function of the nonlinearity. The polynomial kernel generator generates kernels in a multiplier less architecture with polynomial computations in a log domain using a fixed number of adders.

Abstract translation: 多项式核心生成器被配置为从包括通信设备或系统中的非线性分量的发射机路径减轻接收机路径中的非线性。 多项式核心发生器用于产生可用于将非线性建模为应用于非线性的非线性函数的分段多项式逼近的函数的多项式内核。 多项式内核生成器使用固定数量的加法器在日志域中使用多项式计算，在乘数少的架构中生成内核。

公开(公告)号：US09451545B2

公开(公告)日：2016-09-20

申请号：US14583698

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Feng Xue ,  Qinghua Li ,  Wendy C. Wong

IPC: H04L12/26 ,  H04W52/02 ,  H04W52/24 ,  H04W52/28 ,  H04W52/36 ,  H04W52/38 ,  H04W74/08 ,  H04W72/04 ,  H04W74/00

CPC classification number: H04W52/0216 ,  H04W52/0238 ,  H04W52/24 ,  H04W52/286 ,  H04W52/367 ,  H04W52/383 ,  H04W72/0446 ,  H04W74/002 ,  H04W74/0808 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146

Abstract: Embodiments may comprise logic to determine whether a value of a network allocation vector indicates that the apparatus is blocked from transmitting on the medium; logic to transmit a first clear to send packet at a first power level in response to determining that the apparatus is not blocked from transmitting on the medium, the first clear to send packet comprising a flag or bit to indicate the Shading Transmission Starts (STS); logic to receive a second clear to send packet after transmitting the first clear to send packet; and logic to transmit a first data transmission at a second power level after receiving the second clear to send packet, the second power level being less than the first power level.

Abstract translation: 实施例可以包括用于确定网络分配向量的值是否指示该设备被阻止在介质上的传输的逻辑; 响应于确定所述装置不被阻止在所述介质上的传输，以第一功率电平发送第一清除发送分组的逻辑，所述第一清除发送分组包括标志或比特以指示所述着色传输开始（STS） ; 在发送第一个清除发送包之后接收第二个清除发送包的逻辑; 以及在接收到所述第二清除发送分组之后以第二功率电平发送第一数据传输的逻辑，所述第二功率电平小于所述第一功率电平。

公开(公告)号：US11800439B2

公开(公告)日：2023-10-24

申请号：US18067033

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Shahrnaz Azizi ,  Biljana Badic ,  John Browne ,  Dave Cavalcanti ,  Hyung-Nam Choi ,  Thorsten Clevorn ,  Ajay Gupta ,  Maruti Gupta Hyde ,  Ralph Hasholzner ,  Nageen Himayat ,  Simon Hunt ,  Ingolf Karls ,  Thomas Kenney ,  Yiting Liao ,  Christopher MacNamara ,  Marta Martinez Tarradell ,  Markus Dominik Mueck ,  Venkatesan Nallampatti Ekambaram ,  Niall Power ,  Bernhard Raaf ,  Reinhold Schneider ,  Ashish Singh ,  Sarabjot Singh ,  Srikathyayani Srikanteswara ,  Shilpa Talwar ,  Feng Xue ,  Zhibin Yu ,  Robert Zaus ,  Stefan Franz ,  Uwe Kliemann ,  Christian Drewes ,  Juergen Kreuchauf

IPC: H04W4/029 ,  H04W48/16 ,  H04W24/08 ,  H04W48/10 ,  H04W68/00 ,  H04W92/04

CPC classification number: H04W48/16 ,  H04W4/029 ,  H04W24/08 ,  H04W48/10 ,  H04W68/005 ,  H04W92/045

Abstract: A wireless communication device includes a processor configured to select an offload processing task for performance by an edge computing device; cause a baseband modem to establish a direct wireless connection between the wireless communication device and the edge computing device; cause the baseband modem to send first data to the edge computing device via the direct wireless connection; and receive second data from the edge computing device, wherein the second data comprise a result of the offload processing task performed on the first data. The edge computing device includes a processor configured to receive, from a user device, offloaded data to be processed according to an offload processing task; execute the offload processing task on the offloaded data; and cause the radio via the interface to wirelessly send a result of the executed offload processing task via a direct wireless connection with the user device.

公开(公告)号：US11222545B2

公开(公告)日：2022-01-11

申请号：US16455910

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Shu-Ping Yeh ,  Jingwen Bai ,  Feng Xue ,  Mark Davis ,  Shilpa Talwar

IPC: G08G5/00 ,  B64C39/02 ,  G05D1/00 ,  H04B7/185

Abstract: Technologies for providing signal quality based route management for unmanned aerial vehicles include a device that includes circuitry to produce a data set indicative of a wireless communication signal quality at each of multiple locations in a geographic area. The circuitry is also to produce, as a function of the data set and a target wireless communication signal quality, a planned route for a vehicle through the geographic area.