公开(公告)号：US20160365416A1

公开(公告)日：2016-12-15

申请号：US15120803

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  WILLY RACHMADY ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  RAVI PILLARISETTY ,  ROBERT S. CHAU

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

Abstract translation: 实施例包括基于III-V材料的器件，包括：在硅衬底上的基于第一III-V材料的缓冲层; 在第一III-V材料基缓冲层上的第二III-V材料基缓冲层，第二III-V材料包括铝; 以及在第二III-V材料基缓冲层上的基于III-V材料的器件沟道层。 另一实施例包括上述主题，第一和第二III-V材料基缓冲层各自具有等于基于III-V材料的器件沟道层的晶格参数。 本文还包括其它实施例。

公开(公告)号：US20160204246A1

公开(公告)日：2016-07-14

申请号：US14914102

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

Abstract translation: 描述了具有最大化顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍片具有沿着半导体鳍片的长度与一对突出外部部分间隔开的中心突出或凹陷部分。 在半导体翅片的中央突出或凹陷部分上设置包覆层区域。 栅极堆叠设置在包覆层区域上。 源极/漏极区域设置在半导体鳍片的一对突出的外部段中。

公开(公告)号：US20160190319A1

公开(公告)日：2016-06-30

申请号：US14912059

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： JACK T. KAVALIEROS ,  MARKO RADOSAVLJEVIC ,  MATTHEW V. METZ ,  HAN WUI THEN ,  BENJAMIN CHU-KUNG ,  VAN H. LE ,  NILOY MUKHERJEE ,  SANSAPTAK DASGUPTA ,  RAVI PILLARISETTY ,  GILBERT DEWEY ,  ROBERT S. CHAU ,  NANCY M. ZELICK ,  WILLY RACHMADY

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/267 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a lower portion composed of a first semiconductor material with a first lattice constant (L1), and has an upper portion composed of a second semiconductor material with a second lattice constant (L2). A cladding layer is disposed on the upper portion, but not on the lower portion, of the semiconductor fin. The cladding layer is composed of a third semiconductor material with a third lattice constant (L3), wherein L3>L2>L1. A gate stack is disposed on a channel region of the cladding layer. Source/drain regions are disposed on either side of the channel region.

Abstract translation: 描述了具有多层柔性衬底的非平面半导体器件以及制造这种非平面半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍具有由具有第一晶格常数（L1）的第一半导体材料构成的下部，并且具有由具有第二晶格常数（L2）的第二半导体材料构成的上部。 在半导体翅片的上部而不是下部设置包覆层。 包覆层由具有第三晶格常数（L3）的第三半导体材料构成，其中L3> L2> L1。 栅堆叠设置在包层的沟道区上。 源极/漏极区域设置在沟道区域的两侧。