公开(公告)号：US20150076571A1

公开(公告)日：2015-03-19

申请号：US14552959

申请日：2014-11-25

申请人： Intel Corporation

发明人： NILOY MUKHERJEE ,  GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  ROBERT S. CHAU

IPC分类号： H01L29/51 ,  H01L29/78

CPC分类号： H01L29/517 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/41791 ,  H01L29/452 ,  H01L29/456 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

摘要翻译： 与源极或漏极区的接触。 接触件具有导电材料，但是导电材料通过绝缘体与源极或漏极区域分离。

公开(公告)号：US20180047839A1

公开(公告)日：2018-02-15

申请号：US15790907

申请日：2017-10-23

申请人： INTEL CORPORATION

发明人： RAVI PILLARISETTY ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  UDAY SHAH ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  NILOY MUKHERJEE ,  GILBERT DEWEY ,  BEEN Y. JIN ,  ROBERT S. CHAU

IPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/778 ,  H01L29/66 ,  H01L29/267 ,  H01L29/15 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/76 ,  H01L29/51 ,  H01L29/165

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US20160172472A1

公开(公告)日：2016-06-16

申请号：US15043935

申请日：2016-02-15

申请人： INTEL CORPORATION

发明人： RAVI PILLARISETTY ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  UDAY SHAH ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  NILOY MUKHERJEE ,  GILBERT DEWEY ,  BEEN Y. JIN ,  ROBERT S. CHAU

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/78 ,  H01L29/15

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

摘要翻译： 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。

公开(公告)号：US20170221724A1

公开(公告)日：2017-08-03

申请号：US15489569

申请日：2017-04-17

申请人： INTEL CORPORATION

发明人： ANAND S. MURTHY ,  GLENN A. GLASS ,  TAHIR GHANI ,  RAVI PILLARISETTY ,  NILOY MUKHERJEE ,  JACK T. KAVALIEROS ,  ROZA KOTLYAR ,  WILLY RACHMADY ,  MARK Y. LIU

IPC分类号： H01L21/3215 ,  H01L29/06 ,  H01L29/778 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC分类号： H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

公开(公告)号：US20170125524A1

公开(公告)日：2017-05-04

申请号：US15405182

申请日：2017-01-12

申请人： Intel Corporation

发明人： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC分类号： H01L29/10 ,  H01L29/165 ,  H01L29/20 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/267

CPC分类号： H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

摘要： Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

公开(公告)号：US20160359108A1

公开(公告)日：2016-12-08

申请号：US15117594

申请日：2014-03-25

申请人： INTEL CORPORATION

发明人： PRASHANT MAJHI ,  ELIJAH V. KARPOV ,  UDAY SHAH ,  NILOY MUKHERJEE ,  CHARLES C. KUO ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  ROBERT S. CHAU

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/08 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1683

摘要： Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

摘要翻译： 公开了用于形成诸如非平面电阻随机存取存储器（ReRAM或RRAM）单元的非平面电阻存储器单元的技术。 该技术可以用于相对于给定存储器单元空间的平面电阻存储器单元来减少所形成的电压要求和/或电阻（例如在低电阻状态期间的电阻）。 非平面电阻式存储单元包括第一电极，第二电极和设置在第一和第二电极之间的开关层。 在形成非平面电阻式存储单元之后，第二电极可以基本上位于开关层的相对部分之间，并且第一电极可以基本上与开关层的至少两侧相邻。 在一些情况下，氧交换层（OEL）可以设置在开关层与第一和第二电极中的一个之间，以例如增加在电池中引入材料的灵活性。

公开(公告)号：US20150249131A1

公开(公告)日：2015-09-03

申请号：US14707292

申请日：2015-05-08

申请人： Intel Corporation

发明人： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITIKA GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

IPC分类号： H01L29/10 ,  H01L29/04 ,  H01L29/06

CPC分类号： H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

摘要翻译： 本发明的实施例包括外延层，其以允许该层以两个或三个自由度放松的方式直接接触例如纳米线，翅片或支柱。 外延层可以包括在晶体管的沟道区中。 可以去除纳米线，鳍或柱以提供对外延层的更大的访问。 这样做可以允许围绕外延层的顶部，底部和侧壁的“全向栅极”结构。 本文描述了其它实施例。

公开(公告)号：US20180350880A1

公开(公告)日：2018-12-06

申请号：US15777535

申请日：2015-12-23

申请人： INTEL CORPORATION

发明人： PRASHANT MAJHI ,  ELIJAH V. KARPOV ,  RAVI PILLARISETTY ,  UDAY SHAH ,  NILOY MUKHERJEE

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16

CPC分类号： H01L27/2481 ,  G11C11/161 ,  G11C11/165 ,  G11C13/0021 ,  G11C2213/32 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L45/08 ,  H01L45/141 ,  H01L45/146

摘要： A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfOx), tantalum oxide (TaOx), or titanium dioxide (TiOx), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.

公开(公告)号：US20170148982A1

公开(公告)日：2017-05-25

申请号：US15126138

申请日：2014-06-26

申请人： INTEL CORPORATION

发明人： ELIJAH V. KARPOV ,  PRASHANT MAJHI ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  NILOY MUKHERJEE ,  UDAY SHAH ,  ROBERT S. CHAU

IPC分类号： H01L45/00

CPC分类号： H01L45/1206 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are described. In a first example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes an active oxide material region disposed directly between a metal source region and a metal drain region. The device also includes a gate electrode disposed above the active oxide material region. In a second example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes a first active oxide material region spaced apart from a second oxide material region. The device also includes metal input regions disposed on either side of the first and second active oxide material regions. A metal output region is disposed between the first and second active oxide material regions.

公开(公告)号：US20160204246A1

公开(公告)日：2016-07-14

申请号：US14914102

申请日：2013-09-27

申请人： INTEL CORPORATION

发明人： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/267

CPC分类号： H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

摘要： Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

摘要翻译： 描述了具有最大化顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍片具有沿着半导体鳍片的长度与一对突出外部部分间隔开的中心突出或凹陷部分。 在半导体翅片的中央突出或凹陷部分上设置包覆层区域。 栅极堆叠设置在包覆层区域上。 源极/漏极区域设置在半导体鳍片的一对突出的外部段中。