公开(公告)号：US20160179632A1

公开(公告)日：2016-06-23

申请号：US14581859

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Ramon MATAS ,  Roger GRAMUNT ,  Chung-Lun CHAN ,  Benjamin C. CHAFFIN ,  Aditya KESIRAJU ,  Jonathan C. HALL ,  Jesus CORBAL

IPC: G06F11/14

CPC classification number: G06F11/141 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/38 ,  G06F9/3859 ,  G06F9/3865

Abstract: Exemplary aspects are directed toward resolving fault suppression in hardware, which at the same time does not incur a performance hit. For example, when multiple instructions are executing simultaneously, a mask can specify which elements need not be executed. If the mask is disabled, those elements do not need to be executed. A determination is then made as to whether a fault happens in one of the elements that have been disabled. If there is a fault in one of the elements that has been disabled, a state machine re-fetches the instructions in a special mode. More specifically, the state machine determines if the fault is on a disabled element, and if the fault is on a disabled element, then the state machine specifies that the fault should be ignored. If during the first execution there was no mask, if there is an error present during execution, then the element is re-run with the mask to see if the error is a “real” fault.

Abstract translation: 示例性方面涉及解决在硬件中的故障抑制，其同时不会导致性能下降。 例如，当多个指令同时执行时，掩码可以指定不需要执行哪些元素。 如果禁用掩码，则不需要执行这些元素。 然后确定在已经被禁用的元素之一中是否发生故障。 如果其中一个元素中存在故障，则状态机将以特殊模式重新读取指令。 更具体地说，状态机确定故障是否在禁用元件上，如果故障位于禁用元件上，则状态机指定故障应被忽略。 如果在第一次执行期间没有掩码，如果在执行期间存在错误，则使用掩码重新运行该元素，以查看错误是否为“真实”错误。

公开(公告)号：US20230418655A1

公开(公告)日：2023-12-28

申请号：US18207870

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffrey J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/48 ,  G06F9/3001 ,  G06F9/383 ,  G06F9/3004 ,  G06F9/30036

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20220318009A1

公开(公告)日：2022-10-06

申请号：US17573556

申请日：2022-01-11

Applicant: Intel Corporation

Inventor： Venkateswara R. MADDURI ,  Carl MURRAY ,  Elmoustapha OULD-AHMED-VALL ,  Mark J. CHARNEY ,  Robert VALENTINE ,  Jesus CORBAL

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate an unsigned fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

公开(公告)号：US20220291927A1

公开(公告)日：2022-09-15

申请号：US17706428

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Elmoustapha OULD-AHMED-VALL ,  Bret L. TOLL ,  Milind B. GIRKAR ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Rinat RAPPOPORT ,  Jesus CORBAL ,  Stanislav SHWARTSMAN ,  Igor YANOVER ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Dan BAUM ,  Yuri GEBIL

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information

公开(公告)号：US20220164218A1

公开(公告)日：2022-05-26

申请号：US17381521

申请日：2021-07-21

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffrey J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20220058021A1

公开(公告)日：2022-02-24

申请号：US17516023

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Dan BAUM ,  Zeev SPERBER ,  Jesus CORBAL ,  Elmoustapha OULD-AHMED-VALL ,  Bret L. TOLL ,  Mark J. CHARNEY ,  Menachem ADELMAN ,  Barukh ZIV ,  Alexander HEINECKE ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a double word with saturation; computing a dot product of bytes and accumulating in to a dword with saturation, where the input bytes can be signed or unsigned and the dword accumulation has output saturation; etc.

公开(公告)号：US20210132943A1

公开(公告)日：2021-05-06

申请号：US16486960

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Dan BAUM ,  Zeev SPERBER ,  Jesus CORBAL ,  Elmoustapha OULD-AHMED-VALL ,  Bret L. TOLL ,  Mark J. CHARNEY ,  Menachem ADELMAN ,  Barukh ZIV ,  Alexander HEINECKE ,  Simon RUBANOVICH

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a double word with saturation; computing a dot product of bytes and accumulating in to a dword with saturation, where the input bytes can be signed or unsigned and the dword accumulation has output saturation; etc.

公开(公告)号：US20190339972A1

公开(公告)日：2019-11-07

申请号：US16474483

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Dan BAUM ,  Zeev SPERBER ,  Jesus CORBAL ,  Elmoustapha OULD-AHMED-VALL ,  Bret L. TOLL ,  Mark J. CHARNEY ,  Alexander HEINECKE

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to matrix operations. In particular, tile diagonal support is described. For example, a processor is detailed having decode circuitry to decode an instruction having fields for an opcode, a source operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to write the identified source operand to each element along a main diagonal of the identified destination matrix operand.

公开(公告)号：US20170329606A1

公开(公告)日：2017-11-16

申请号：US15608738

申请日：2017-05-30

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Mark J. CHARNEY ,  Jesus CORBAL ,  Milind B. GIRKAR ,  Elmoustapha OULD-AHMED-VALL ,  Bret L. TOLL ,  Robert VALENTINE

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109

Abstract: Systems, apparatuses, and methods of performing in a computer processor broadcasting data in response to a single vector packed broadcasting instruction that includes a source writemask register operand, a destination vector register operand, and an opcode. In some embodiments, the data of the source writemask register is zero extended prior to broadcasting.