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    MEMORYLESS WEIGHT STORAGE HARDWARE FOR NEURAL NETWORKS
    31.
    发明申请
    MEMORYLESS WEIGHT STORAGE HARDWARE FOR NEURAL NETWORKS 审中-公开

    公开(公告)号：US20190042913A1

    公开(公告)日：2019-02-07

    申请号：US15884001

    申请日：2018-01-30

    Applicant: Intel Corporation

    Inventor： Phil Knag ,  Gregory Kengho Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Ram Kumar Krishnamurthy

    IPC: G06N3/04

    Abstract: Various systems, devices, and methods for operating on a data sequence. A system includes a set of circuits that form an input layer to receive a data sequence; first hardware computing units to transform the data sequence, the first hardware computing units connected using a set of randomly selected weights, a first hardware computing unit to: receive an input from a second hardware computing unit, determine a weight of a connection between the first and second hardware computing units using an identifier of the second hardware computing unit and a fixed random weight generator, and operate on the input using the weight to determine a state of the first hardware computing unit; and second hardware computing units to operate on states of the first computing units to generate an output based on the data sequence.

    EVENT DRIVEN AND TIME HOPPING NEURAL NETWORK
    32.
    发明申请
    EVENT DRIVEN AND TIME HOPPING NEURAL NETWORK 审中-公开

    公开(公告)号：US20180189648A1

    公开(公告)日：2018-07-05

    申请号：US15394976

    申请日：2016-12-30

    Applicant: Intel Corporation

    Inventor： Abhronil Sengupta ,  Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Phil Knag

    IPC: G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/08 ,  G06N3/049

    Abstract: In one embodiment, a processor is to store a membrane potential of a neural unit of a neural network; and calculate, at a particular time-step of the neural network, a change to the membrane potential of the neural unit occurring over multiple time-steps that have elapsed since the last time-step at which the membrane potential was updated, wherein each of the multiple time-steps that have elapsed since the last time-step is associated with at least one input to the neural unit that affects the membrane potential of the neural unit.

    Compute near memory convolution accelerator
    35.
    发明授权
    Compute near memory convolution accelerator 有权

    公开(公告)号：US11726950B2

    公开(公告)日：2023-08-15

    申请号：US16586975

    申请日：2019-09-28

    Applicant: Intel Corporation

    Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Raghavan Kumar ,  Ram Krishnamurthy

    IPC: G06F15/80 ,  G06F17/15 ,  G06N3/063

    CPC classification number: G06F15/8046 ,  G06F17/153 ,  G06N3/063

    Abstract: A compute near memory (CNM) convolution accelerator enables a convolutional neural network (CNN) to use dedicated acceleration to achieve efficient in-place convolution operations with less impact on memory and energy consumption. A 2D convolution operation is reformulated as 1D row-wise convolution. The 1D row-wise convolution enables the CNM convolution accelerator to process input activations row-by-row, while using the weights one-by-one. Lightweight access circuits provide the ability to stream both weights and input rows as vectors to MAC units, which in turn enables modules of the CNM convolution accelerator to implement convolution for both [1×1] and chosen [n×n] sized filters.

    Weight prefetch for in-memory neural network execution
    36.
    发明授权
    Weight prefetch for in-memory neural network execution 有权

    公开(公告)号：US11347994B2

    公开(公告)日：2022-05-31

    申请号：US16160466

    申请日：2018-10-15

    Applicant: Intel Corporation

    Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

    IPC: G06F3/06 ,  G06N3/04 ,  G06F12/0875 ,  G06N3/063

    Abstract: The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nth layer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)st layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)st layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.

    Compute near memory with backend memory
    37.
    发明授权
    Compute near memory with backend memory 有权

    公开(公告)号：US11251186B2

    公开(公告)日：2022-02-15

    申请号：US16827542

    申请日：2020-03-23

    Applicant: Intel Corporation

    Inventor： Abhishek Sharma ,  Noriyuki Sato ,  Sarah Atanasov ,  Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Ram Krishnamurthy ,  Hui Jae Yoo ,  Van H. Le

    IPC: G11C11/24 ,  H01L27/108 ,  H01L27/12 ,  G11C11/4096

    Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

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