公开(公告)号：US09941898B1

公开(公告)日：2018-04-10

申请号：US15391575

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Rotem Banin ,  Elias Nassar ,  Inbar Falkov ,  Eyal Fayneh ,  Ofir Degani ,  Sebastian Sievert

IPC: H03M1/50 ,  H03M1/82 ,  H03K5/131 ,  H03L7/091 ,  H03K19/21 ,  H03M1/66 ,  H03K5/00

CPC classification number: H03M1/82 ,  H03K5/131 ,  H03K19/21 ,  H03K2005/00058 ,  H03L7/091 ,  H03M1/662

Abstract: Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.

公开(公告)号：US09791834B1

公开(公告)日：2017-10-17

申请号：US15393115

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Elias Nassar ,  Samer Nassar ,  Eyal Fayneh ,  Rotem Banin ,  Ofir Degani ,  Inbar Falkov

IPC: H03M1/50 ,  G04F10/00

CPC classification number: G04F10/005 ,  G04G5/00

Abstract: A system includes a digital-to-time converter (DTC) to generate output signals with phase offsets set by a plurality of DTC input values and a time-to-digital converter (TDC) operatively coupled to the DTC, wherein the TDC has a lower resolution than the DTC. The system also includes a processing component operatively coupled to the DTC and the TDC. The processing device, for each of a plurality of TDC thresholds, determines a DTC input value corresponding to a respective TDC threshold. The processing device may then generate a calibration function based on the determined DTC input values and corresponding TDC thresholds.