公开(公告)号：US10594294B2

公开(公告)日：2020-03-17

申请号：US15088830

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Baris Bicen ,  Telesphor Kamgaing ,  Vijay K. Nair ,  Georgios C. Dogiamis ,  Johanna M. Swan ,  Valluri R. Rao

IPC: H03H9/13 ,  H03H9/36

Abstract: Embodiments of the invention include a waveguide structure that includes a first piezoelectric transducer that is positioned in proximity to a first end of a cavity of an organic substrate. The first piezoelectric transducer receives an input electrical signal and generates an acoustic wave to be transmitted with a transmission medium. A second piezoelectric transducer is positioned in proximity to a second end of the cavity. The second piezoelectric transducer receives the acoustic wave from the transmission medium and generates an output electrical signal.

公开(公告)号：US10291283B2

公开(公告)日：2019-05-14

申请号：US15088996

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Feras Eid ,  Adel A. Elsherbini ,  Georgios C. Dogiamis ,  Vijay K. Nair ,  Johanna M. Swan ,  Valluri R. Rao

IPC: H04B1/48 ,  H03H7/38 ,  H01H57/00 ,  H03H15/00

Abstract: Embodiments of the invention include a tunable radio frequency (RF) communication module that includes a transmitting component having at least one tunable component and a receiving component having at least one tunable component. The tunable RF communication module includes at least one piezoelectric switching device coupled to at least one of the transmitting and receiving components. The at least one piezoelectric switching device is formed within an organic substrate having organic material and is designed to tune at least one tunable component of the tunable RF communication module.

公开(公告)号：US10134727B2

公开(公告)日：2018-11-20

申请号：US14738799

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

IPC: H01L29/00 ,  H01L27/06 ,  H01L29/94 ,  H01L29/04 ,  H01L29/778 ,  H01L29/10 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8252 ,  H01L21/8258

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

公开(公告)号：US20160365341A1

公开(公告)日：2016-12-15

申请号：US14738799

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/20 ,  H01L29/10 ,  H01L29/205 ,  H01L29/94 ,  H01L29/778

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66181 ,  H01L29/7787 ,  H01L29/94 ,  H01L29/945

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract translation: 集成了至少一个具有高击穿电压（BV）的III-N MOS电容器的III-N高压MOS电容器和片上系统（SoC）解决方案，以实现高压和/或高功率电路。 可以实现超过4V的击穿电压，避免了RFIC和/或PMIC中的串联耦合电容的任何需要。 在实施例中，包括其中在低于0V的阈值电压下形成二维电子气（2DEG）的GaN层的耗尽型III-N电容器与IV族晶体管架构单片集成，例如平面和非平面硅CMOS晶体管技术 。 在实施例中，蚀刻硅衬底以提供形成GaN层和III-N势垒层的（111）外延生长表面。 在实施例中，沉积高K电介质层，并且电容器端子触点被制成2DEG并且在电介质层上。

公开(公告)号：US20160043471A1

公开(公告)日：2016-02-11

申请号：US14918508

申请日：2015-10-20

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Valluri R. Rao ,  Ofir Degani

IPC: H01Q9/04 ,  H01Q21/00 ,  H01Q1/52

CPC classification number: H01Q9/045 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01P11/00 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q1/526 ,  H01Q21/0006 ,  Y10T29/49018

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming a package structure comprising a discrete antenna disposed on a back side of a device, wherein the discrete antenna comprises an antenna substrate, a through antenna substrate via vertically disposed through the antenna substrate. A through device substrate via that is vertically disposed within the device is coupled with the through antenna substrate via, and a package substrate is coupled with an active side of the device.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括形成包括设置在设备的背侧的分立天线的封装结构，其中分立天线包括天线基板，通过天线基板垂直设置的通过天线基板。 垂直设置在器件内的穿通器件衬底通孔经由天线衬底与封装衬底耦合，并且封装衬底与器件的有源侧耦合。