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31.发明公开公开(公告)号：US20230195683A1
公开(公告)日：2023-06-22
申请号：US17558564
申请日：2021-12-21
Applicant: Intel Corporation
Inventor： Vikram Suresh , Tao Zhou , Shashank Shekhar , Amitkumar Patel , Sanu Mathew
IPC: G06F15/78 , G06F1/3287
CPC classification number: G06F15/78 , G06F1/3287 , G06F15/7807
Abstract: Methods and apparatus relating to techniques utilizing fine-grained bitcoin engine deactivation for yield recovery, performance, and/or power management are described. In an embodiment, a configurable compute tile comprising a plurality of cryptocurrency mining engines. Logic circuitry causes deactivation of one or more cryptocurrency mining engines from the plurality of cryptocurrency mining engines based at least in part on a request for deactivation of the one or more cryptocurrency mining engines. The logic circuitry adjusts a nonce search resolution for one or more active cryptocurrency mining engines of the plurality of cryptocurrency mining engines in response to the request for deactivation. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20230004681A1
公开(公告)日：2023-01-05
申请号：US17930326
申请日：2022-09-07
Applicant: Intel Corporation
Inventor： Vikram Suresh , Raghavan Kumar , Sanu Mathew
Abstract: A method comprises generating, during an enrollment process conducted in a controlled environment, a dark bit mask comprising a plurality of state information values derived from a plurality of entropy sources at a plurality of operating conditions for an electronic device, and using at least a portion of the plurality of state information values to generate a set of challenge-response pairs for use in an authentication process for the electronic device.
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公开(公告)号：US20220058167A1
公开(公告)日：2022-02-24
申请号：US17128836
申请日：2020-12-21
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sanu Mathew , Raghavan Kumar
Abstract: Techniques and mechanisms to facilitate Bitcoin mining operations which support version rolling. In an embodiment, Bitcoin mining circuitry comprises a first scheduler, a first digest, a second scheduler and a second digest arranged in a pipeline configuration. Hash circuitry calculates a first plurality of hashes each based on first bits of a Merkle root, and on a different respective identifier of a Bitcoin protocol version. The first scheduler generates first message schedules each based on second bits of the Merkle root, and on a different respective nonce value. In another embodiment, the first scheduler successively provides the first message schedules to the first digest, wherein, for each such providing of one of the first message schedules, the first digest, second scheduler and second digest successively generate second hashes each based on the provided one of the first message schedules, and on a different respective one of the first hashes.
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公开(公告)号：US11240039B2
公开(公告)日：2022-02-01
申请号：US16455921
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sanu Mathew , Manoj Sastry , Santosh Ghosh , Raghavan Kumar , Rafael Misoczki
Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.
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公开(公告)号：US20190325166A1
公开(公告)日：2019-10-24
申请号：US16456339
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sanu Mathew , Rafael Misoczki , Santosh Ghosh , Raghavan Kumar , Manoj Sastry , Andrew H. Reinders
Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.
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Patent Agency Ranking
公开(公告)号：US20190319782A1
公开(公告)日：2019-10-17
申请号：US16455950
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： SANTOSH GHOSH , Vikram Suresh , Sanu Mathew , Manoj Sastry , Andrew H. Reinders , Raghavan Kumar , Rafael Misoczki
Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.
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37.发明申请公开(公告)号：US20190044739A1
公开(公告)日：2019-02-07
申请号：US15941050
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Manoj Sachdev , Vikram Suresh , Sanu Mathew , Sudhir Satpathy
Abstract: An embodiment of a semiconductor package apparatus may include technology to generate a first output from a physically unclonable function (PUF) based on a challenge, modify the challenge based on the first output, and generate a response based on the modified challenge. Some embodiments may additionally or alternatively include technology to change a read sequence of the PUF based on an output of the PUF. Some embodiments may additionally or alternatively include technology to vary a latency of a linear feedback shift register based on an output from the PUF. Other embodiments are disclosed and claimed.
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38.发明申请公开(公告)号：US20190044699A1
公开(公告)日：2019-02-07
申请号：US16021526
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： Sudhir Satpathy , Sanu Mathew , Vikram Suresh
IPC: H04L9/06
Abstract: Methods and apparatus for a reconfigurable Galois Field (GF) Sbox unit for Camellia, AES, and SM4 hardware accelerator are described. In one embodiment, a modified Substitute box (Sbox) leverages a common field of GF to incorporate a multi-cipher mode of operation. The hybrid Sbox design can reduce area and/or energy consumption. Other embodiments are also described and claimed.
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39.发明公开公开(公告)号：US20230195511A1
公开(公告)日：2023-06-22
申请号：US17710746
申请日：2022-03-31
Applicant: Intel Corporation
Inventor： Vikram Suresh , Amitkumar Patel , Chandra S. Katta , Sanu Mathew , Long Sheng
CPC classification number: G06F9/4843 , H04L9/0643 , G06F12/124
Abstract: Methods and apparatus relating to techniques for an energy-efficient cryptocurrency (e.g., Bitcoin) mining hardware accelerator with a spatially shared message scheduler are described. In an embodiment, a plurality of mining engines perform one or more operations for a cryptocurrency. A single scheduler processes a first portion of a message for two or more mining engines of the plurality of mining engines and pre-computation logic circuitry processes a second portion of the message for the two or more mining engines. Other embodiments are also disclosed and claimed.
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公开(公告)号：US11575521B2
公开(公告)日：2023-02-07
申请号：US16455967
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Rafael Misoczki , Vikram Suresh , David Wheeler , Santosh Ghosh , Manoj Sastry
Abstract: In one example an apparatus comprises accelerator logic to pre-compute at least a portion of a message representative, hash logic to generate the message representative based on an input message, and signature logic to generate a signature to be transmitted in association with the message representative, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and determine whether the message representative satisfies a target threshold allocation of computational costs between a cost to generate the signature and a cost to verify the signature. Other examples may be described.
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