公开(公告)号：US20220199792A1

公开(公告)日：2022-06-23

申请号：US17691926

申请日：2022-03-10

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Biswajeet GUHA ,  Mark ARMSTRONG ,  William HSU ,  Tahir GHANI ,  Swaminathan SIVAKUMAR

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20220093589A1

公开(公告)日：2022-03-24

申请号：US17026047

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  William HSU ,  Biswajeet GUHA ,  Martin WEISS ,  Apratim DHAR ,  William T. BLANTON ,  John H. IRBY, IV ,  James F. BONDI ,  Michael K. HARPER ,  Charles H. WALLACE ,  Tahir GHANI ,  Benedict A. SAMUEL ,  Stefan DICKERT

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20210305430A1

公开(公告)日：2021-09-30

申请号：US16833208

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Stephen SNYDER ,  Biswajeet GUHA ,  William HSU ,  Urusa ALAAN ,  Tahir GHANI ,  Michael K. HARPER ,  Vivek THIRTHA ,  Shu ZHOU ,  Nitesh KUMAR

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

公开(公告)号：US20210202479A1

公开(公告)日：2021-07-01

申请号：US16727355

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Biswajeet GUHA ,  William HSU ,  Bruce BEATTIE ,  Tahir GHANI

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.

公开(公告)号：US20210193836A1

公开(公告)日：2021-06-24

申请号：US16719222

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Ayan KAR ,  Nicholas THOMSON ,  Benjamin ORR ,  Nathan JACK ,  Kalyan KOLLURU ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.