公开(公告)号：US20230163215A1

公开(公告)日：2023-05-25

申请号：US18094285

申请日：2023-01-06

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Stephen SNYDER ,  Biswajeet GUHA ,  William HSU ,  Urusa ALAAN ,  Tahir GHANI ,  Michael K. HARPER ,  Vivek THIRTHA ,  Shu ZHOU ,  Nitesh KUMAR

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/165 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/7856 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/165 ,  H01L21/02293 ,  H01L29/0649 ,  H01L29/0847 ,  H01L21/022 ,  H01L29/1091 ,  H01L29/78696 ,  H01L29/7851

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

公开(公告)号：US20220416044A1

公开(公告)日：2022-12-29

申请号：US17359440

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Nitesh KUMAR ,  Mohammed HASAN ,  Vivek THIRTHA ,  Nikhil MEHTA ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/08 ,  H01L27/092

Abstract: Gate-all-around integrated circuit structures having nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of horizontal nanowires. The epitaxial growth occurs inside a mold confinement, and due the mold, the lateral wingspan of the wingspan of the epitaxial growth is limited. Also the mold causes the epitaxial source or drain structures to exhibit substantially vertical opposing sidewalls and a top surface having a generally mushroom shape over a top of a dielectric layer.

公开(公告)号：US20220416042A1

公开(公告)日：2022-12-29

申请号：US17358478

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： William HSU ,  Leonard P. GULER ,  Vivek THIRTHA ,  Nitesh KUMAR ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having reduced gate height structures and subfins, and method of fabricating gate-all-around integrated circuit structures having reduced gate height structures, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a subfin, and an isolation structure on either side of the subfin. A gate stack is over the plurality of nanowires, around individual nanowires, and over the subfin. Gate spacers are on either side of the gate stack, and a dielectric capping material is inside the gate spacers with shoulder portions inside the gate stack.

公开(公告)号：US20220416041A1

公开(公告)日：2022-12-29

申请号：US17357895

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Mohammad HASAN ,  William HSU ,  Biswajeet GUHA ,  Oleg GOLONZKA ,  Tahir GHANI ,  Vivek THIRTHA ,  Nitesh KUMAR

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

Abstract: Embodiments disclosed herein include semiconductor devices and methods of making semiconductor devices. In an embodiment, a semiconductor device comprises a substrate, where the substrate is a dielectric material, and a vertical stack of semiconductor channels over the substrate. In an embodiment, the semiconductor device further comprises a source at a first end of the semiconductor channels, a drain at a second end of the semiconductor channels, and a barrier between a bottom surface of the source and the substrate.

公开(公告)号：US20210305430A1

公开(公告)日：2021-09-30

申请号：US16833208

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Stephen SNYDER ,  Biswajeet GUHA ,  William HSU ,  Urusa ALAAN ,  Tahir GHANI ,  Michael K. HARPER ,  Vivek THIRTHA ,  Shu ZHOU ,  Nitesh KUMAR

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.