公开(公告)号：US11144387B2

公开(公告)日：2021-10-12

申请号：US16398076

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  William A. Stevens, Jr. ,  Michael T. Klinglesmith ,  Mikal Hunsaker

IPC: G06F11/10 ,  G06F13/16 ,  G06F13/42

Abstract: Embodiments include a serial bus controller that may be coupled to an in band serial peripheral interface (SPI) link, to request a write of data and a subsequent read of the data from a memory device and in response to the request to read the data, receive a bit error report and optionally correct the bit error over the in band SPI link. Embodiments include a memory device, e.g., a flash memory device, to detect and report the bit error over the in band SPI link, where the flash memory device, in response to a request to write and/or erase data, calculates or determines an error correction code (ECC) and stores corresponding parity data. In embodiments, after receiving a subsequent request to read the data, the flash memory device accesses the stored parity data to check the ECC for a bit error and if a bit error is detected, reports the detected bit error over the in band SPI link. Other embodiments may be described and claimed.

公开(公告)号：US20190251010A1

公开(公告)日：2019-08-15

申请号：US16394929

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Aditya Bhutada ,  Zhenyu Zhu ,  Mazen Gedeon

IPC: G06F11/22 ,  G06F11/30 ,  G06F11/07

CPC classification number: G06F11/2221 ,  G06F11/0772 ,  G06F11/0778 ,  G06F11/0784 ,  G06F11/3051

Abstract: Embodiments may include apparatus, systems, and methods associated with an Enhanced Serial Peripheral Interface (eSPI) channel interface to couple to a data bus to link an eSPI master device to an eSPI slave device. In embodiments, the eSPI master device includes an eSPI device controller and is coupled to the channel interface and transmits a notification of a crash event, e.g., a catastrophic error (CATERR), via packet-based signaling, such as a virtual wire (VW) over the data bus to allow the eSPI master device to transmit the notification of the crash event without allocation of a dedicated wire signal for the notification between the eSPI master device and the eSPI slave device. Other embodiments may be described and/or claimed.

公开(公告)号：US20190228160A1

公开(公告)日：2019-07-25

申请号：US16370566

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Mikal Hunsaker ,  Mark Feuerstraeter ,  Asad Azam ,  Zhenyu Zhu ,  Navtej Singh

IPC: G06F21/57 ,  G05B9/02 ,  G05B19/042

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust.

公开(公告)号：US20170154009A1

公开(公告)日：2017-06-01

申请号：US15070481

申请日：2016-03-15

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Nobuyuki Suzuki ,  Anoop Mukker ,  Daniel Nemiroff ,  David W. Vogel

IPC: G06F13/42 ,  G06F1/08 ,  G06F1/24 ,  G06F9/44 ,  G06F1/32

CPC classification number: G06F13/4282 ,  G06F1/08 ,  G06F1/24 ,  G06F1/3287 ,  G06F9/4411

Abstract: An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a reset sequence and an initialization of a link configuration register. The method also includes driving a high voltage signal to the clock lanes and the data lanes. The method further includes driving a bus turn-around (BTA) sequence on the data lanes. The method also includes detecting that the BTA is acknowledged by a host controller.