公开(公告)号：US10380032B2

公开(公告)日：2019-08-13

申请号：US15454243

申请日：2017-03-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Uwe Brandt ,  Markus Helms ,  Christian Jacobi ,  Markus Kaltenbach ,  Thomas Koehler ,  Frank Lehnert

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/455

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

公开(公告)号：US10372457B2

公开(公告)日：2019-08-06

申请号：US15802725

申请日：2017-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael K. Gschwind ,  Christian Jacobi ,  Anthony Saporito ,  Chung-Lung K. Shum

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0862

Abstract: A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.

公开(公告)号：US20190227932A1

公开(公告)日：2019-07-25

申请号：US16372997

申请日：2019-04-02

Applicant: International Business Machines Corporation

Inventor： Gregory W. Alexander ,  Brian D. Barrick ,  Thomas W. Fox ,  Christian Jacobi ,  Anthony Saporito ,  Somin Song ,  Aaron Tsai

IPC: G06F12/0811 ,  G06F12/0813 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0804 ,  G06F12/0855

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

公开(公告)号：US10318415B2

公开(公告)日：2019-06-11

申请号：US15609469

申请日：2017-05-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Giles R. Frazier ,  Michael K. Gschwind ,  Christian Jacobi ,  Younes Manton ,  Anthony Saporito ,  Chung-Lung K. Shum

IPC: G06F12/02 ,  G06F12/0802

Abstract: A garbage collection facility is provided for memory management within a computer. The facility implements, in part, grouping of infrequently accessed data units in a designated transient memory area, and includes designating an area of the memory as a transient memory area and an area as a conventional memory area, and counting, for each data unit in the transient or conventional memory areas a number of accesses to the data unit. The counting provides a respective access count for each data unit. For each data unit in the transient memory area or the conventional memory area, a determination is made whether the respective access count is below a transient threshold ascertained to separate frequently accessed data units and infrequently used data units. Data units with respective access counts below the transient threshold are grouped together as transient data units within the transient memory area.

公开(公告)号：US10303575B2

公开(公告)日：2019-05-28

申请号：US15402412

申请日：2017-01-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Christian Jacobi ,  Daniel V. Rosa ,  Anthony Saporito ,  Donald W. Schmidt

IPC: G06F9/48 ,  G06F9/50 ,  G06F11/30 ,  G06F11/34

Abstract: A facility is provided for collecting time-slice-instrumentation information during processing unit execution. The facility counts, at least in part, occurrence of a specified processing unit event during a time-slice of processing unit execution. The counted events occurring during a first interval of execution and a second interval of execution of the time-slice are retained. The first interval of execution is earlier in the time-slice than the second interval of execution, and the counted events facilitate adjusting performance of the processing unit. In an embodiment, the time-slice is a contiguous period of time of processing unit execution, and the specified processing unit event includes a cache event. The processing unit may interleave processing of multiple different units of work across multiple contiguous time-slices, and during a single time-slice, a single unit of work of the multiple different units of work is processed by the processing unit.

公开(公告)号：US10303545B1

公开(公告)日：2019-05-28

申请号：US15827285

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Patrick J. Meaney ,  Christian Jacobi ,  Barry M. Trager

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/15 ,  G11C29/52

Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols in order to facilitate Redundant Array of Independent Memory (RAIM) functionalities for the memory modules. A host receives and decodes the ECC symbols and executes RAIM operations. The host and the memory modules are coupled by a number of channels, one channel per each set of the memory devices.

公开(公告)号：US10282305B2

公开(公告)日：2019-05-07

申请号：US15212570

申请日：2016-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christian Borntraeger ,  Jonathan D. Bradbury ,  Lisa Cranton Heller ,  Christian Jacobi ,  Martin Schwidefsky

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/1027

Abstract: Selective purging of entries of structures associated with address translation. A request to purge entries of a structure associated with address translation is obtained. Based on obtaining the request, a determination is made as to whether selective purging of the structure associated with address translation is to be performed. Based on determining that selective purging is to be performed, one or more entries of the structure associated with address translation are purged. The selectively purging includes clearing the one or more entries of the structure associated with address translation for a host of the computing environment and leaving one or more entries of one or more guest operating systems in the structure associated with address translation. The one or more guest operating systems are managed by the host.

公开(公告)号：US20190114234A1

公开(公告)日：2019-04-18

申请号：US16213165

申请日：2018-12-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dan F. Greiner ,  Christian Jacobi ,  Timothy J. Slegel

IPC: G06F11/14 ,  G06F9/46 ,  G06F11/36 ,  G06F13/40 ,  G06F9/38

Abstract: Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted.

公开(公告)号：US10241924B2

公开(公告)日：2019-03-26

申请号：US15212436

申请日：2016-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. Bradbury ,  Christian Jacobi ,  Anthony Saporito

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/02 ,  G06F12/1081 ,  G06F12/14 ,  G06F12/1036 ,  G06F12/121

Abstract: A marking capability is used to provide an indication of whether a block of memory is being used by a guest control program to back an address translation structure. The marking capability includes setting an indicator in one or more locations associated with the block of memory. In a further aspect, the marking capability includes a purging capability that limits the purging of translation look-aside buffers and other such structures based on the marking.

公开(公告)号：US20190079872A1

公开(公告)日：2019-03-14

申请号：US15812570

申请日：2017-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. Bradbury ,  Michael K. Gschwind ,  Christian Jacobi ,  Chung-Lung K. Shum

IPC: G06F12/0862 ,  G06F12/0811 ,  G06F13/16 ,  G06F12/084 ,  G06F11/30

Abstract: Controlling a rate of prefetching based on bus bandwidth. A determination is made as to whether a rate of prefetching data from memory into a cache is to be changed. This determination is based on bus utilization. Based on determining that the rate is to be changed, the rate of prefetching is changed.