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31.发明申请公开(公告)号：US20200343597A1
公开(公告)日：2020-10-29
申请号：US16397497
申请日：2019-04-29
IPC分类号： H01M10/42 , H01M10/0565 , H01M10/058 , H01M4/134 , H01M4/131
摘要： An interfacial additive layer for decreasing the interfacial resistance/impedance of a silicon based electrode-containing device such as, for example, an energy storage device or a micro-resistor, is disclosed. The interfacial additive, which is composed of evaporated lithium fluoride, is formed between a silicon based electrode and a solid polymer electrolyte layer of the device. The evaporated lithium fluoride serves as ion conductive layer. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the silicon based electrode interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device.
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公开(公告)号：US10777842B2
公开(公告)日：2020-09-15
申请号：US16026473
申请日：2018-07-03
IPC分类号： H01M10/0525 , H01M10/0567 , H01M4/66 , H01M4/525 , H01M10/058 , H01M4/505 , H01M4/02
摘要： Rechargeable lithium-ion batteries that have a high-capacity are provided. The lithium-ion batteries contain an anode structure that is of unitary construction and includes a non-porous region and a porous region including a top porous layer (Porous Region 1) having a first thickness and a first porosity, and a bottom porous layer (Porous Region 2) located beneath the top porous layer and forming an interface with the non-porous region. At least an upper portion of the non-porous region and the entirety of the porous region are composed of silicon, and the bottom porous layer has a second thickness that is greater than the first thickness, and a second porosity that is greater than the first porosity.
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公开(公告)号：US20200251784A1
公开(公告)日：2020-08-06
申请号：US16848394
申请日：2020-04-14
发明人： Ning Li , Joel P. de Souza , Yun Seog Lee , Devendra K. Sadana
IPC分类号： H01M10/0583 , H01M10/0525 , H01M4/04 , H01M4/36 , H01M10/0562
摘要： An all solid-state lithium-based thin-film battery is provided. The all solid-state lithium-based thin-film battery includes a battery material stack of, from bottom to top, an anode-side electrode, an anode region, an aluminum oxide interfacial layer, a solid-state electrolyte layer, a cathode layer, and a cathode-side electrode layer. The all solid-state lithium-based thin-film battery stack is formed by first forming the anode-side of the battery stack and thereafter forming the cathode-side. All solid-state lithium-based thin-film batteries including the aluminum oxide interfacial layer located between the anode region and the solid-state electrolyte layer have improved performance, high capacity, and high reliability.
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公开(公告)号：US10601033B2
公开(公告)日：2020-03-24
申请号：US15721001
申请日：2017-09-29
IPC分类号： H01M4/36 , H01M10/052 , H01M2/26 , H01M2/30 , H01M10/00 , H01M4/62 , H01M4/13 , H01M4/139 , H01M10/04 , H01M10/0585 , H01M4/70 , H01M10/058 , H01M10/42 , H01M10/0564
摘要： A high-capacity and a high-performance rechargeable battery is provided by forming a rechargeable battery stack that includes a spalled material structure that includes a spalled cathode material layer that has at least one textured surface and a stressor layer that has at least one textured surface. The stressor layer serves as a cathode current collector of the rechargeable battery stack. The at least one textured surface of the spalled cathode material layer forms a large interface area between the cathode and electrolyte which is formed above the spalled cathode material layer. The large interface area between the cathode and the electrolyte reduces interface resistance within the rechargeable battery stack.
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公开(公告)号：US10546971B2
公开(公告)日：2020-01-28
申请号：US15867121
申请日：2018-01-10
发明人： Joel P. de Souza , Ning Li , Devendra Sadana , Yao Yao
IPC分类号： H01L31/18 , H01L21/265 , H01L31/0304 , H01L21/266 , H01L31/103
摘要： Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor material that includes a first type of majority carrier. A doping enhancement layer is formed over a region of the semiconductor material, wherein the doping enhancement layer includes a first type of material. A dopant is accelerated sufficiently to drive the dopant through the doping enhancement layer into the region of the semiconductor material. Accelerating the dopant through the doping enhancement layer also drives some of the first type of material from the doping enhancement layer into the region of the semiconductor material. The dopant within the region and the first type of material within the region contribute to the region having a second type of majority carrier.
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公开(公告)号：US20190326429A1
公开(公告)日：2019-10-24
申请号：US16502685
申请日：2019-07-03
发明人： Devendra Sadana , Dechao Guo , Joel P. de Souza , Ruqiang Bao , Stephen w. Bedell , Shogo Mochizuki , Gen Tsutsui , Hemanth Jagannathan , Marinus Hopstaken
摘要： Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
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公开(公告)号：US10381479B2
公开(公告)日：2019-08-13
申请号：US15663133
申请日：2017-07-28
发明人： Devendra Sadana , Dechao Guo , Joel P. de Souza , Ruqiang Bao , Stephen W. Bedell , Shogo Mochizuki , Gen Tsutsui , Hemanth Jagannathan , Marinus Hopstaken
IPC分类号： H01L29/78 , H01L29/66 , H01L21/762 , H01L21/02 , H01L29/161 , H01L29/04
摘要： Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
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公开(公告)号：US10276816B2
公开(公告)日：2019-04-30
申请号：US14567805
申请日：2014-12-11
IPC分类号： H01L51/42 , H01L31/18 , H01L27/14 , H01L31/112 , H01L31/20
摘要： A semiconductor device that includes a layer of highly crystalline semiconductor material positioned on an insulating substrate. The semiconductor device also includes a source structure and a drain structure positioned on the layer of highly crystalline semiconductor material. The semiconductor device also includes a photoelectric element positioned on the layer of highly crystalline semiconductor material. The photoelectric element forms an electrical junction with the layer of highly crystalline semiconductor material. The photoelectric element is positioned between the source structure and the drain structure. The photoelectric element is also electrically floating.
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公开(公告)号：US20190115626A1
公开(公告)日：2019-04-18
申请号：US15787453
申请日：2017-10-18
IPC分类号： H01M10/0585 , H01M4/36
摘要： High-capacity and high-performance rechargeable batteries containing a cathode material layer having an improved surface roughness is provided. A cathode material layer is provided in which at least an upper portion of the cathode material layer is composed of nanoparticles (i.e., particles having a particle size less than 0.1 μm). In some embodiments, a lower (or base) portion of the cathode material layer is composed of particles whose particle size is greater than the nanoparticles that form the upper portion of the cathode material layer. In other embodiments, the entirety of the cathode material layer is composed of the nanoparticles. In either embodiment, a conformal layer of a dielectric material can be disposed on a topmost surface of the upper portion of the cathode material layer. The presence of the conformal layer of dielectric material can further improve the smoothness of the cathode material layer.
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40.发明授权公开(公告)号：US10204823B2
公开(公告)日：2019-02-12
申请号：US15857042
申请日：2017-12-28
发明人： Stephen W. Bedell , Stephan A. Cohen , Joel P. de Souza , Karen A. Nummy , Daniel J. Poindexter , Devendra K. Sadana
IPC分类号： H01L21/70 , H01L29/66 , H01L21/762 , H01L21/324
摘要： A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.
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