公开(公告)号：US20230091621A1

公开(公告)日：2023-03-23

申请号：US17480791

申请日：2021-09-21

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Shogo Mochizuki ,  Juntao Li ,  Choonghyun Lee

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08

摘要： A semiconductor structure includes a substrate comprising a semiconductor material, and a fin on the substrate. The fin includes a first portion formed from the semiconductor material and a second portion including a channel region. The first portion has a first thickness and the second portion has a second thickness greater than the first thickness. A spacer is disposed on sides of the first portion of the fin.

公开(公告)号：US11482612B2

公开(公告)日：2022-10-25

申请号：US17136852

申请日：2020-12-29

申请人： International Business Machines Corporation

发明人： Shogo Mochizuki ,  Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/225 ,  H01L21/8238

摘要： A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, sacrificial spacer layers are formed on the plurality of fins, and portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins are removed. Bottom source/drain regions are grown in at least part of an area where the portions of the semiconductor substrate were removed, and sacrificial epitaxial layers are grown on the bottom source/drain regions. The method also includes diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins. The sacrificial epitaxial layers are removed, and bottom spacers are formed in at least part of an area where the sacrificial epitaxial layers were removed.

公开(公告)号：US11239360B2

公开(公告)日：2022-02-01

申请号：US16743880

申请日：2020-01-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Shogo Mochizuki ,  Brent A. Anderson ,  Hemanth Jagannathan ,  Junli Wang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/56 ,  H01L21/8234 ,  H01L29/417

摘要： A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.

公开(公告)号：US11189724B2

公开(公告)日：2021-11-30

申请号：US16169589

申请日：2018-10-24

申请人： International Business Machines Corporation

发明人： Dexin Kong ,  Kangguo Cheng ,  Shogo Mochizuki

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L29/51 ,  H01L21/768 ,  H01L21/02 ,  H01L21/324 ,  H01L29/08

摘要： A metal is formed into an opening that is located in an interlayer dielectric (ILD) material that laterally surrounds a semiconductor fin of a partially fabricated vertical transistor and on a physically exposed topmost surface of the semiconductor fin. A patterned material stack of, and from bottom to top, a membrane and a doped amorphous semiconductor material layer is formed on the metal and a topmost surface of the ILD material. A metal induced layer exchange anneal is then employed in which the metal and doped semiconductor material change places such that the doped semiconductor material is in direct contact with the topmost surface of the semiconductor fin. The exchanged doped semiconductor material, which provides a top source/drain structure of the vertical transistor, may have a different crystalline orientation than the topmost surface of the semiconductor fin.

公开(公告)号：US11183593B2

公开(公告)日：2021-11-23

申请号：US16592389

申请日：2019-10-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Huimei Zhou ,  Su Chen Fan ,  Shogo Mochizuki ,  Peng Xu ,  Nicolas J. Loubet

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L27/06 ,  H01L29/08

摘要： A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

公开(公告)号：US11063147B2

公开(公告)日：2021-07-13

申请号：US16733832

申请日：2020-01-03

申请人： International Business Machines Corporation

发明人： Shogo Mochizuki ,  Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/324 ,  H01L29/66 ,  H01L29/49 ,  H01L29/08 ,  H01L21/768 ,  H01L29/786 ,  H01L29/167 ,  H01L21/02 ,  H01L21/28 ,  H01L29/161

摘要： Techniques for forming bottom source and drain extensions in VTFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming a liner at a base of the fins having a higher diffusivity for dopants than the fins; forming sidewall spacers alongside an upper portion of the fins; forming bottom source/drains on the liner at the base of the fins including the dopants; annealing the wafer to diffuse the dopants from the bottom source/drains, through the liner, into the base of the fins to form bottom extensions; removing the sidewall spacers; forming bottom spacers on the bottom source/drains; forming gate stacks alongside the fins above the bottom spacers; forming top spacers above the gate stacks; and forming top source/drains above the top spacers at tops of the fins. A VTFET device is also provided.

公开(公告)号：US11011624B2

公开(公告)日：2021-05-18

申请号：US16505411

申请日：2019-07-08

申请人： International Business Machines Corporation

发明人： Shogo Mochizuki ,  Michael P. Belyansky ,  Choonghyun Lee

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/786

摘要： A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.

公开(公告)号：US10916633B2

公开(公告)日：2021-02-09

申请号：US16167770

申请日：2018-10-23

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Shogo Mochizuki ,  Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li

IPC分类号： H01L29/76 ,  H01L29/161 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L21/768 ,  H01L21/3065 ,  H01L29/49

摘要： A method for forming the semiconductor device that includes forming an etch mask covering a drain side of the gate structure and the silicon containing fin structure; etching a source side of the silicon containing fin structure adjacent to the channel region; and forming a germanium containing semiconductor material on an etched sidewall of the silicon containing fin structure adjacent to the channel region. Germanium from the germanium containing semiconductor material is diffused into the channel region to provide a graded silicon germanium region in the channel region having germanium present at a highest concentration in the channel region at the source end of the channel region and a germanium deficient concentration at the drain end of the channel region.

公开(公告)号：US10892368B2

公开(公告)日：2021-01-12

申请号：US16406390

申请日：2019-05-08

申请人： International Business Machines Corporation

发明人： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki

IPC分类号： H01L29/786 ,  H01L29/775 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

摘要： Embodiments of the invention are directed to a method that includes forming a nanosheet stack over a substrate. The nanosheet stack includes a first channel nanosheet having a first end region, a second end region, and a central region positioned between the first end region and the second end region. The first end region, the second end region, and the central region each includes a first type of semiconductor material, wherein, when the first type of semiconductor material is at a first temperature, the first type of semiconductor material has a first diffusion coefficient for a dopant. The central region is converted to a second type of semiconductor material, wherein, when the second type of semiconductor material is at the first temperature, the second type of semiconductor material has a second diffusion coefficient for the dopant.

公开(公告)号：US10763343B2

公开(公告)日：2020-09-01

申请号：US16369990

申请日：2019-03-29

申请人： International Business Machines Corporation

发明人： Alexander Reznicek ,  Shogo Mochizuki

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/49 ,  H01L21/768 ,  H01L21/225 ,  H01L21/02 ,  H01L21/28 ,  H01L23/535 ,  H01L29/165

摘要： A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.