-
公开(公告)号:US20230094258A1
公开(公告)日:2023-03-30
申请号:US18061149
申请日:2022-12-02
发明人: Ruqiang Bao , Koji Watanabe
IPC分类号: H01L27/092 , H01L29/78 , H01L29/66 , H01L21/02 , H01L29/06
摘要: A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer.
-
公开(公告)号:US11476418B2
公开(公告)日:2022-10-18
申请号:US17114605
申请日:2020-12-08
发明人: Injo Ok , Ruqiang Bao , Andrew Herbert Simon , Kevin W. Brew , Nicole Saulnier , Iqbal Rashid Saraf , Prasad Bhosale
IPC分类号: H01L45/00
摘要: A semiconductor structure may include a heater surrounded by a second dielectric layer, a projection liner on top of the second dielectric layer, and a phase change material layer above the projection liner. A top surface of the projection liner may be substantially flush with a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.
-
公开(公告)号:US11456219B2
公开(公告)日:2022-09-27
申请号:US16849156
申请日:2020-04-15
发明人: Ruqiang Bao , Dechao Guo , Junli Wang , Heng Wu
IPC分类号: H01L29/423 , H01L21/8238 , H01L27/092 , H01L21/3215 , H01L21/28 , H01L29/78 , H01L29/06
摘要: A technique relates to a semiconductor device. An N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work function metal, an outer work function metal, a first nanosheet including an inner channel surface having a first threshold voltage, and a second nanosheet including an outer channel surface having a second threshold voltage. The outer work function metal is modified so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).
-
4.
公开(公告)号:US20220238682A1
公开(公告)日:2022-07-28
申请号:US17718989
申请日:2022-04-12
发明人: Ruqiang Bao , Huiming Bu
IPC分类号: H01L29/423 , H01L21/02 , H01L21/8238 , H01L27/092 , H01L21/28 , H01L29/06 , H01L29/66
摘要: A method for fabricating a semiconductor device includes forming an interfacial layer and a dielectric layer on a base structure and around channels of a first gate-all-around field-effect transistor (GAA FET) device within a first region and a second GAA FET device within a second region, forming at least a scavenging metal layer in the first and second regions, and performing an anneal process after forming at least one cap layer.
-
5.
公开(公告)号:US11251285B2
公开(公告)日:2022-02-15
申请号:US16553912
申请日:2019-08-28
IPC分类号: H01L29/78 , H01L29/66 , H01L29/786 , H01L29/423 , H01L21/324 , H01L21/02 , H01L29/49
摘要: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.
-
公开(公告)号:US11245020B2
公开(公告)日:2022-02-08
申请号:US16745100
申请日:2020-01-16
发明人: Ruqiang Bao , Michael A. Guillorn , Terence Hook , Robert R. Robison , Reinaldo Vega , Tenko Yamashita
IPC分类号: H01L29/423 , H01L29/66 , H01L29/78 , H01L29/49 , H01L29/06 , H01L29/775 , B82Y10/00 , H01L29/786
摘要: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
-
公开(公告)号:US20220013521A1
公开(公告)日:2022-01-13
申请号:US16946856
申请日:2020-07-09
发明人: Chen Zhang , Dechao Guo , Junli Wang , Ruilong Xie , Kangguo Cheng , Juntao Li , Chanro Park , Ruqiang Bao , Sung Dae Suk , Lan Yu , Heng Wu
IPC分类号: H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/8238 , H01L29/66
摘要: An embodiment of the invention may include a semiconductor structure and method of manufacturing. The semiconductor structure may include a top channel and a bottom channel, wherein the top channel includes a plurality of vertically oriented channels. The bottom channel includes a plurality of horizontally oriented channels. The semiconductor structure may include a gate surrounding the top channel and the bottom channel. The semiconductor structure may include spacers located on each side of the gate. A first spacer includes a dielectric material located between the plurality of vertically oriented channels. A second spacer includes a dielectric material located between the plurality of horizontally oriented channels. This may enable spacer formation between the vertical spacers.
-
公开(公告)号:US20220005807A1
公开(公告)日:2022-01-06
申请号:US17481497
申请日:2021-09-22
发明人: Ruqiang Bao , Koji Watanabe
IPC分类号: H01L27/092 , H01L29/78 , H01L29/66 , H01L21/02 , H01L29/06
摘要: A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer.
-
公开(公告)号:US11152489B2
公开(公告)日:2021-10-19
申请号:US16681038
申请日:2019-11-12
发明人: Ruqiang Bao , Kisup Chung , Andrew M. Greene , Sivananda K. Kanakasabapathy , David L. Rath , Indira P. V. Seshadri , Rajasekhar Venigalla
IPC分类号: H01L29/66 , H01L21/768 , H01L23/535 , H01L29/78 , H01L29/08 , H01L29/417 , H01L21/8234 , H01L27/088
摘要: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.
-
公开(公告)号:US10957646B2
公开(公告)日:2021-03-23
申请号:US16782311
申请日:2020-02-05
发明人: Benjamin D. Briggs , Cornelius Brown Peethala , Michael Rizzolo , Koichi Motoyama , Gen Tsutsui , Ruqiang Bao , Gangadhara Raja Muthinti , Lawrence A. Clevenger
IPC分类号: H01L23/532 , H01L21/02 , H01L21/48 , H01L21/768 , H01L21/306
摘要: A semiconductor wafer has a top surface, a dielectric insulator, a plurality of narrow copper wires, a plurality of wide copper wires, an optical pass through layer over the top surface, and a self-aligned pattern in a photo-resist layer. The plurality of wide copper wires and the plurality of narrow copper wires are embedded in a dielectric insulator. The width of each wide copper wire is greater than the width of each narrow copper. An optical pass through layer is located over the top surface. A self-aligned pattern in a photo-resist layer, wherein photo-resist exists only in areas above the wide copper wires, is located above the optical pass through layer.
-
-
-
-
-
-
-
-
-