公开(公告)号：US20220198310A1

公开(公告)日：2022-06-23

申请号：US17129977

申请日：2020-12-22

Applicant: International Business Machines Corporation

Inventor： Peter Mueller ,  Thomas Morf

IPC: G06N10/00 ,  G01R33/00 ,  G01R33/035

Abstract: A computer-implemented method of reducing an impact of stray magnetic fields on components of a quantum computing chip is disclosed. The computer implemented method includes applying a first current signal to a first component of a quantum computing chip, whereby the first component generates a stray magnetic field impacting an operation of a second component of the quantum computing chip. The computer implemented method further includes applying a compensation current signal to a shielding circuit of the quantum computing chip, the compensation current signal generated according to a predetermined function of the first signal, to magnetically shield the second component from the stray magnetic field generated by the first component.

公开(公告)号：US20200184363A1

公开(公告)日：2020-06-11

申请号：US16788439

申请日：2020-02-12

Applicant: International Business Machines Corporation

Inventor： Peter Mueller ,  Thomas Morf

IPC: G06N10/00 ,  H03H11/54 ,  H03K17/92 ,  H03H11/04

Abstract: A quantum computer hardware apparatus may include a first stage, which is connected to one or more signal generators, and a second stage adapted to be cooled down at a lower temperature than the first stage. Superconducting qubits are arranged in the second stage. The signal generators are configured, each, to generate radio frequency (RF) signals to drive the qubits, in operation. The apparatus may further include an intermediate stage between the first stage and the second stage, wherein the intermediate stage comprises one or more coolable filters, the latter configured for thermalizing RF signals from the signal generators. Related methods for thermalizing radio frequency signals in a quantum computer hardware apparatus are also disclosed.

公开(公告)号：US20170068475A1

公开(公告)日：2017-03-09

申请号：US15353772

申请日：2016-11-17

Applicant: International Business Machines Corporation

Inventor： Danny Harnik ,  MICHAEL FACTOR ,  DMITRY SOTNIKOV ,  PAULA TA-SHMA ,  Lukas Kull ,  Thomas Morf

IPC: G06F3/06 ,  H03M13/15 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/065 ,  G06F3/067 ,  G06F11/1088 ,  G06F11/1092 ,  H03M13/154

Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include detecting multiple sets of storage objects stored in a data facility including multiple server racks, each of the server racks including a plurality of server computers, each of the storage objects in each set being stored in a separate one of the server racks and including one or more data objects and one or more protection objects. A specified number of the storage objects are identified in a given server rack, each of the identified storage objects being stored in a separate one of the server computers, and one or more server computers in the given server rack not storing any of the identified storage objects are identified. Finally, in the identified one or more server computers, an additional protection object is created and managed for the identified storage objects.

Abstract translation: 方法，计算系统和计算机程序产品实现本发明的实施例，包括检测存储在包括多个服务器机架的数据设施中的多组存储对象，每个服务器机架包括多个服务器计算机，每个存储对象 每个集合存储在服务器机架中的单独的一个中并且包括一个或多个数据对象和一个或多个保护对象。 在给定的服务器机架中识别指定数量的存储对象，每个标识的存储对象被存储在单独的一个服务器计算机中，并且给定服务器机架中的一个或多个服务器计算机不存储任何所识别的存储 识别对象。 最后，在所标识的一个或多个服务器计算机中，为所标识的存储对象创建并管理附加保护对象。

公开(公告)号：US20160190670A1

公开(公告)日：2016-06-30

申请号：US15062239

申请日：2016-03-07

Applicant: International Business Machines Corporation

Inventor： Roi Carmon ,  Danny Elad ,  Noam Kaminski ,  Ofer Markish ,  Thomas Morf ,  Evgeny Shumaker

IPC: H01P5/08

CPC classification number: H01P5/107 ,  H01P5/10

Abstract: An apparatus providing a direct chip to waveguide transition, comprising: one or more waveguides, a chip partially embedding each of the waveguides at a transition area positioned at a narrow side of each waveguide, and a transmitting element disposed at each of the transition areas, thereby providing one or more simultaneous, direct transitions between the chip and the waveguides.

Abstract translation: 一种向波导转换提供直接芯片的装置，包括：一个或多个波导，将芯片中的每一个部分地嵌入位于每个波导的窄边的过渡区域的芯片，以及设置在每个过渡区域的发送元件， 从而在芯片和波导之间提供一个或多个同时直接的转换。

公开(公告)号：US20140284483A1

公开(公告)日：2014-09-25

申请号：US14287872

申请日：2014-05-27

Applicant: International Business Machines Corporation

Inventor： Dan Corcos ,  Danny Elad ,  Noam Kaminski ,  Bernhard Klein ,  Lukas Kull ,  Thomas Morf

IPC: G01J5/20

CPC classification number: G01J5/20 ,  G01J5/0837 ,  G01N21/3581 ,  H01Q21/26

Abstract: There is provided a high responsivity device for thermal sensing in a Terahertz (THz) radiation detector. A load impedance connected to an antenna heats up due to the incident THz radiation received by the antenna. The heat generated by the load impedance is sensed by a thermal sensor such as a transistor. To increase the responsivity of the sense device without increasing the thermal mass, the device is located underneath a straight portion of an antenna arm. The transistor runs substantially the entire length of the antenna arm alleviating the problem caused by placing large devices on the side of the antenna and the resulting large additional thermal mass that must be heated. This boosts the responsivity of the pixel while retaining an acceptable level of noise and demanding a dramatically smaller increase in the thermal time constant.

Abstract translation: 在太赫兹（THz）辐射检测器中提供了用于热感测的高响应度装置。 连接到天线的负载阻抗由于天线接收到的入射太赫兹辐射而加热。 由负载阻抗产生的热量由诸如晶体管的热传感器来感测。 为了增加感测装置的响应度而不增加热质量，该装置位于天线臂的直线部分的下方。 晶体管基本上在天线臂的整个长度上延伸，从而减轻了将大型器件放置在天线侧面所引起的问题以及由此产生的必须被加热的大量附加热质。 这提高了像素的响应度，同时保持了可接受的噪声水平，并且要求热时间常数的显着更小的增加。

公开(公告)号：US20140117241A1

公开(公告)日：2014-05-01

申请号：US13663502

申请日：2012-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dan Corcos ,  Danny Elad ,  Noam Kaminski ,  Bernhard Klein ,  Lukas Kull ,  Thomas Morf

IPC: G01J5/08

CPC classification number: G01J5/0809 ,  G01J5/0837 ,  G01J5/20 ,  H01Q19/108 ,  H01Q19/30

Abstract: A novel and useful THz radiation detector comprising a suspended dipole antenna and a plurality of reflectors for achieving low thermal mass and high electrical performance. The reflectors used in the antenna do not physical contact the dipole element and are used to shape the radiation pattern in similar fashion as obtained by well-known Yagi-Uda reflectors. The dipole element is connected directly to a load resister for generating heat which is sensed by a sensing transistor. The lack of a mechanical connection to the dipole antenna element prevents any increase in the thermal capacitance of the antenna.

Abstract translation: 一种新颖有用的THz辐射检测器，包括悬挂偶极天线和多个用于实现低热质量和高电性能的反射器。 在天线中使用的反射器不与物理接触偶极子元件，并用于以与已知的Yagi-Uda反射器所获得的相似的方式来形成辐射图案。 偶极元件直接连接到用于产生由感测晶体管感测的热量的负载电阻器。 与偶极天线元件的机械连接的缺乏防止天线的热电容的任何增加。

公开(公告)号：US12278598B2

公开(公告)日：2025-04-15

申请号：US17651829

申请日：2022-02-21

Applicant: International Business Machines Corporation

Inventor： Mridula Prathapan ,  Thomas Morf ,  Peter Mueller ,  Marcel A. Kossel ,  Bogdan Cezar Zota ,  Pier Andrea Francese

IPC: H03F1/26 ,  G06N10/20 ,  H03F1/02 ,  H03F1/56

Abstract: Provided is a low noise amplifier circuit for a quantum computer. The low noise amplifier circuit comprises a plurality of input stages, a shared output stage, and a voltage controller. Each input stage is coupled to one or more qubits. The shared output stage is coupled to the plurality of input stages. The voltage controller is coupled to the plurality of input stages and the shared output stage. The voltage controller is configured to selectively activate an input stage of the plurality of input stages in order to read a qubit coupled to the input stage.

公开(公告)号：US20240315149A1

公开(公告)日：2024-09-19

申请号：US18183200

申请日：2023-03-14

Applicant: International Business Machines Corporation

Inventor： Andrea Ruffino ,  Mridula Prathapan ,  Peter Mueller ,  John Francis Bulzacchelli ,  Sudipto Chakraborty ,  Thomas Morf

IPC: H10N69/00 ,  G06N10/40 ,  H01L29/66 ,  H01P3/08 ,  H01P7/08 ,  H10N60/85

CPC classification number: H10N69/00 ,  G06N10/40 ,  H01L29/66977 ,  H01P3/08 ,  H01P7/08 ,  H10N60/85

Abstract: The present disclosure relates to a cryogenic integrated circuit, the circuit being a Complementary metal-oxide-semiconductor (CMOS) or Bipolar CMOS (BiCMOS) stacked circuit. The circuit comprises: a substrate, and a resonator formed on the substrate. The resonator comprises a meandered inductor formed in a specific metal layer of the stack, wherein the specific metal layer, when cooled below a critical temperature, becomes superconducting.

公开(公告)号：US20240281691A1

公开(公告)日：2024-08-22

申请号：US18171447

申请日：2023-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bogdan Cezar Zota ,  Eunjung Cha ,  Thomas Morf ,  Mridula Prathapan ,  Peter Mueller ,  Alberto Ferraris

IPC: G06N10/40

CPC classification number: G06N10/40

Abstract: Embodiments including a semiconductor device circuit for biasing gates of a qubit device as well as a method for operating the device are disclosed. The embodiments may include a multiplexed array of capacitor cells, where each capacitor cell includes a transistor-controlled capacitor, where each capacitor is connected between a drain of a respective transistor and ground, where each source of all transistors of all capacitor cells are connected to a common control point, and where each gate of the transistors of the capacitor cells are individually voltage controllable. The embodiment may include a charging unit connected to the common control point, and a discharging unit connected to the common control point, where the charging unit and the discharging unit are alternatively activatable.

公开(公告)号：US20230283290A1

公开(公告)日：2023-09-07

申请号：US17652960

申请日：2022-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marcel A. Kossel ,  Pier Andrea Francese ,  Abdullah Serdar Yonar ,  Mridula Prathapan ,  Thomas Morf

IPC: H03M1/50 ,  H03K5/135

CPC classification number: H03M1/50 ,  H03K5/135

Abstract: Disclosed herein is a hierarchical time step generator circuit configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator comprises: a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal; a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals; and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.