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公开(公告)号:US20240315149A1
公开(公告)日:2024-09-19
申请号:US18183200
申请日:2023-03-14
Applicant: International Business Machines Corporation
Inventor: Andrea Ruffino , Mridula Prathapan , Peter Mueller , John Francis Bulzacchelli , Sudipto Chakraborty , Thomas Morf
Abstract: The present disclosure relates to a cryogenic integrated circuit, the circuit being a Complementary metal-oxide-semiconductor (CMOS) or Bipolar CMOS (BiCMOS) stacked circuit. The circuit comprises: a substrate, and a resonator formed on the substrate. The resonator comprises a meandered inductor formed in a specific metal layer of the stack, wherein the specific metal layer, when cooled below a critical temperature, becomes superconducting.
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公开(公告)号:US20240274326A1
公开(公告)日:2024-08-15
申请号:US18489634
申请日:2023-10-18
Applicant: SuperMag Technology (Shanghai) Ltd.
Inventor: Yue ZHAO , Chunjiang GUO , Yue WU , Wei WU
IPC: H01B12/02 , B23K1/08 , B23K1/20 , B23K101/34 , B23K101/38 , B23K103/04 , B23K103/12 , H10N60/85
CPC classification number: H01B12/02 , B23K1/08 , B23K1/20 , H10N60/85 , B23K2101/35 , B23K2101/38 , B23K2103/05 , B23K2103/12
Abstract: A method for fabricating a lamination structure of a second-generation high-temperature superconducting (2G-HTS) tape is provided. Suitable lamination tapes are selected and subjected to local oxidation on side to form a locally oxidized region having a target pattern. The lamination tapes and a to-be-laminated 2G-HTS tape are sequentially arranged, where the locally-oxidized side of each of the lamination tapes faces toward the 2G-HTS tape. The lamination tapes and the to-be-laminated 2G-HTS tape are simultaneously immersed in a molten solder pool, and subjected to reel-to-reel squeezing lamination to form the desired lamination structure. A lamination structure fabricated by the method is also provided.
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公开(公告)号:US20240249770A1
公开(公告)日:2024-07-25
申请号:US18587872
申请日:2024-02-26
Applicant: PsiQuantum Corp,
Inventor: Faraz Najafi
CPC classification number: G11C11/44 , H10N60/30 , H10N60/83 , H10N60/84 , H10N69/00 , H10N60/01 , H10N60/85
Abstract: An example memory cell includes a superconducting loop configured to receive a write current and form a persistent current that stores a data bit in the superconducting loop. The example memory cell further includes a superconducting wire coupled to the superconducting loop and configured to selectively read-out the data bit in the superconducting loop in response to a control signal. An example method of reading data from the memory cell includes receiving, at the superconducting loop, a write current to store a data bit in a superconducting loop, and forming a persistent current that circulates in the superconducting loop as a stored data bit. The example method further includes, in accordance with a control signal, transferring, via a superconducting wire of the memory cell that is coupled to the superconducting loop, at least a portion of the persistent current to an output of the memory cell.
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公开(公告)号:US12040398B2
公开(公告)日:2024-07-16
申请号:US17613992
申请日:2020-05-26
Applicant: UNIVERSIDADE DO PORTO
CPC classification number: H01L29/78391 , H10N60/85 , H10N60/99
Abstract: The present invention relates to a one-electrode cell and series of two or more cells as a device at temperatures from below to above room temperature comprising a very high permittivity ferroelectric.
In a device constituted by one or more ferroelectricity-induced superconductor cells, the cells do not have to be in physical contact with one another; one terminal can be connected to a first cell and the other connected to a third cell without physical contact between any of the three cells. With the spontaneous and dynamic alignment of the dipoles of the ferroelectric, a potential difference is induced in different points of the surface of the cell, cells or device and a current can be harvested by conductor-terminals.
The present invention can be used for contactless charging of energy storage devices and as a part of several components or products.-
公开(公告)号:US11972794B2
公开(公告)日:2024-04-30
申请号:US17967778
申请日:2022-10-17
Applicant: PsiQuantum Corp.
Inventor: Faraz Najafi
CPC classification number: G11C11/44 , H10N60/30 , H10N60/83 , H10N60/84 , H10N69/00 , H10N60/01 , H10N60/85
Abstract: An electronic device includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material includes a first wire and a loop that is (1) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state.
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公开(公告)号:US11930722B2
公开(公告)日:2024-03-12
申请号:US17727784
申请日:2022-04-24
Applicant: Ambature, Inc.
Inventor: Douglas J. Gilbert , Timothy S. Cale
CPC classification number: H10N60/858 , H10N60/01 , H10N60/0296 , H10N60/85 , Y10T29/49014 , Y10T428/24322 , Y10T428/31678
Abstract: Operational characteristics of an high temperature superconducting (“HTS”) film comprised of an HTS material may be improved by depositing a modifying material onto appropriate surfaces of the HTS film to create a modified HTS film. In some implementations of the invention, the HTS film may be in the form of a “c-film.” In some implementations of the invention, the HTS film may be in the form of an “a-b film,” an “a-film” or a “b-film.” The modified HTS film has improved operational characteristics over the HTS film alone or without the modifying material. Such operational characteristics may include operating in a superconducting state at increased temperatures, carrying additional electrical charge, operating with improved magnetic properties, operating with improved mechanic properties or other improved operational characteristics. In some implementations of the invention, the HTS material is a mixed-valence copper-oxide perovskite, such as, but not limited to YBCO. In some implementations of the invention, the modifying material is a conductive material that bonds easily to oxygen, such as, but not limited to, chromium.
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公开(公告)号:US11877523B2
公开(公告)日:2024-01-16
申请号:US17369732
申请日:2021-07-07
Applicant: Microsoft Technology Licensing, LLC
Inventor: Roman Lutchyn , Michael Freedman , Andrey Antipov
IPC: H01L29/20 , H10N60/84 , H03K3/38 , G06N10/00 , B82Y10/00 , H01L29/66 , H01L29/06 , H10N60/01 , H10N60/30 , H10N60/85 , H10N60/10
CPC classification number: H10N60/84 , B82Y10/00 , G06N10/00 , H01L29/0673 , H01L29/66977 , H03K3/38 , H10N60/01 , H10N60/128 , H10N60/30 , H10N60/85 , H01L29/20
Abstract: Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.
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公开(公告)号:US20230420161A1
公开(公告)日:2023-12-28
申请号:US18244492
申请日:2023-09-11
Applicant: David B. SMATHERS , Paul R. AIMONE
Inventor: David B. SMATHERS , Paul R. AIMONE
Abstract: In various embodiments, superconducting wires incorporate diffusion barriers composed of Nb alloys or Nb—Ta alloys that resist internal diffusion and provide superior mechanical strength to the wires.
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公开(公告)号:US11793089B2
公开(公告)日:2023-10-17
申请号:US16577539
申请日:2019-09-20
Applicant: Microsoft Technology Licensing, LLC
Inventor: Candice Fanny Thomas , Michael James Manfra
CPC classification number: H10N60/805 , G06N10/00 , H10N60/0912 , H10N60/12 , H10N60/85
Abstract: A hybrid heterostructure includes a semiconductor layer comprising indium antimonide, a superconductor layer comprising aluminum, and a screening layer between the semiconductor layer and the superconductor layer, the screening layer comprising indium arsenide. By including a screening layer of indium arsenide between the semiconductor layer of indium antimonide and the superconductor layer of aluminum, a high-performance and durable hybrid heterostructure suitable for use in quantum computing devices is provided.
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公开(公告)号:US11758827B2
公开(公告)日:2023-09-12
申请号:US16664123
申请日:2019-10-25
Applicant: Bruker EAS GmbH
Inventor: Carl Buehler , Vital Abaecherli , Bernd Sailer , Klaus Schlenga , Manfred Thoener , Matheus Wanior
CPC classification number: H10N60/0128 , B22F5/12 , B22F7/04 , H01B12/06 , H10N60/0156 , H10N60/85
Abstract: A monofilament (100) for producing an Nb3Sn-containing superconductor wire (33) includes a powder core (1) with an Sn-containing powder, a reaction tube (3) composed of an Nb alloy that includes Nb and at least one further alloy component X. The powder core is disposed within the reaction tube. The monofilament also includes at least one source (4) for at least one partner component Pk. A respective source includes one or more source structures at a unitary radial position in the monofilament. The alloy component X and the partner component Pk form precipitates XPk on reaction annealing of the monofilament in which Sn from the powder core and Nb from the reaction tube react to produce Nb3Sn. The powder core is disposed in a moderation tube, which in turn is disposed within the reaction tube. This provides a monofilament for a powder-in-tube based Nb3Sn-containing superconductor wire with improved current carrying capacity.
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