公开(公告)号：US12191382B2

公开(公告)日：2025-01-07

申请号：US17542485

申请日：2021-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cezar Bogdan Zota ,  Thomas Morf ,  Eunjung Cha ,  Peter Mueller

IPC: H01L29/778 ,  H01L29/12 ,  H01L29/66

Abstract: A superconductor transistor structure includes a source electrode and a drain electrode on a same plane as the source electrode. There is a channel region on top of the source and drain electrodes and configured to carry a current. A gate structure comprising a metallic material is on top of the channel region. The source and drain are located on a side that is opposite to that of the gate structure, with respect to the channel region.

公开(公告)号：US11916568B2

公开(公告)日：2024-02-27

申请号：US17652960

申请日：2022-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marcel A. Kossel ,  Pier Andrea Francese ,  Abdullah Serdar Yonar ,  Mridula Prathapan ,  Thomas Morf

IPC: H03M1/50 ,  H03K5/135

CPC classification number: H03M1/50 ,  H03K5/135

Abstract: A hierarchical time step generator circuit is configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator includes a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.

公开(公告)号：US11811418B2

公开(公告)日：2023-11-07

申请号：US17652957

申请日：2022-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marcel A. Kossel ,  Pier Andrea Francese ,  Abdullah Serdar Yonar ,  Mridula Prathapan ,  Thomas Morf

IPC: H03M1/12 ,  H04B1/16

CPC classification number: H03M1/124 ,  H03M1/121 ,  H04B1/16

Abstract: Disclosed herein is an analog-to-digital converter circuit configured for digitizing an analog input signal. The analog-to-digital converter comprises an analog input configured for receiving the analog input signal. The analog-to-digital converter circuit further comprises at least one sub-ADC connected to the analog input signal, wherein the at least one sub-ADC is configured to output at least one encoded output vector in response to receiving the analog input signal. The analog-to-digital converter circuit further comprises a lookup circuit comprising a nested lookup table. The lookup circuit is configured to select an output value from the nested lookup table using the at least one encoded output vector, wherein the lookup circuit is configured to provide the output value as the digitization of the analog input signal.

公开(公告)号：US11735578B2

公开(公告)日：2023-08-22

申请号：US17564157

申请日：2021-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Peter Mueller ,  Thomas Morf ,  Mridula Prathapan ,  Matthias Mergenthaler

IPC: H01L27/02 ,  G06N10/00 ,  H01L29/872 ,  H02H9/04

CPC classification number: H01L27/0251 ,  G06N10/00 ,  H01L29/872 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit is configured to protect a target circuit that operates in a cryogenic temperature is provided. The ESD protection circuit connects a terminal of the target circuit and a ground potential with no connection to a bias potential. When the ESD protection circuit receives a voltage potential at the terminal of the target circuit, the ESD protection circuit (i) disallows electrical current to flow through from the received voltage potential when the device is at a cryogenic temperature and (ii) allows electrical current to flow through from the received voltage potential when the device is at a room temperature.

公开(公告)号：US20230197842A1

公开(公告)日：2023-06-22

申请号：US17555961

申请日：2021-12-20

Applicant: International Business Machines Corporation

Inventor： Cezar Bogdan Zota ,  Eunjung Cha ,  Thomas Morf ,  Peter Mueller

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/66462

Abstract: One or more systems, devices, methods of use and/or methods of fabrication provided herein relate to a high-electron-mobility transistor with a gate electrode below the channel. According to one embodiment, a device comprises a source electrode and a drain electrode coupled to a top surface of a high-electron-mobility transistor (HEMT) heterostructure, and a gate electrode located in contact with an underside of the HEMT heterostructure

公开(公告)号：US20230139805A1

公开(公告)日：2023-05-04

申请号：US17453499

申请日：2021-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Thomas Morf ,  Cezar Bogdan Zota ,  Peter Mueller ,  Pier Andrea Francese ,  Marcel A. Kossel ,  Matthias Braendli ,  Mridula Prathapan

IPC: G06F15/82 ,  G06N10/40

Abstract: The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.

公开(公告)号：US10891557B2

公开(公告)日：2021-01-12

申请号：US16788439

申请日：2020-02-12

Applicant: International Business Machines Corporation

Inventor： Peter Mueller ,  Thomas Morf

IPC: G06N10/00 ,  H03K17/92 ,  H03H11/54 ,  H03H11/04 ,  H03F19/00

Abstract: A quantum computer hardware apparatus may include a first stage, which is connected to one or more signal generators, and a second stage adapted to be cooled down at a lower temperature than the first stage. Superconducting qubits are arranged in the second stage. The signal generators are configured, each, to generate radio frequency (RF) signals to drive the qubits, in operation. The apparatus may further include an intermediate stage between the first stage and the second stage, wherein the intermediate stage comprises one or more coolable filters, the latter configured for thermalizing RF signals from the signal generators. Related methods for thermalizing radio frequency signals in a quantum computer hardware apparatus are also disclosed.

公开(公告)号：US20140117236A1

公开(公告)日：2014-05-01

申请号：US13663508

申请日：2012-10-30

Applicant: International Business Machines Corporation

Inventor： Dan Corcos ,  Danny Elad ,  Noam Kaminski ,  Bernhard Klein ,  Lukas Kull ,  Thomas Morf

IPC: G01J5/20

CPC classification number: G01J5/20 ,  G01J5/0837 ,  H01Q1/2283

Abstract: A novel and useful THz radiation detector comprising a suspended wideband planar skirt antenna for achieving low thermal mass and high electrical performance. The antenna comprises only the perimeter or “skirt” of the antenna. The antenna has multiple loops where each loop comprises a conductor that covers the perimeter or skirt and includes multiple inner and outer arms. The total length of each loop has a length substantially one wavelength. One or more ports or load impedances are connected at the center of the antenna and shared by one or more loops. A thermal sensor detects the heat generated in the load resister and converts the heat energy to an electrical signal which is transmitted to read out circuitry via signal lines that run together with a holding arm. The holding arm functions as both a path for the read out signals as well as providing mechanical support for and effectively suspending the antenna.

Abstract translation: 一种新颖有用的THz辐射检测器，其包括用于实现低热质量和高电性能的悬挂宽带平面裙状天线。 天线仅包括天线的周边或“裙部”。 天线具有多个环，其中每个环包括覆盖周边或裙部的导体，并且包括多个内部和外部臂。 每个环的总长度具有基本上一个波长的长度。 一个或多个端口或负载阻抗连接在天线的中心并由一个或多个环路共享。 热传感器检测负载电阻中产生的热量，并将热能转换成电信号，电信号通过与保持臂一起运行的信号线传输到读出电路。 保持臂用作读出信号的路径，以及为天线提供机械支撑并有效地悬挂天线。

公开(公告)号：US12095473B2

公开(公告)日：2024-09-17

申请号：US18053940

申请日：2022-11-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Abdullah Serdar Yonar ,  Pier Andrea Francese ,  Marcel A. Kossel ,  Mridula Prathapan ,  Matthias Braendli ,  Thomas Morf

IPC: H03M1/50 ,  H03M1/10 ,  H03M1/12

CPC classification number: H03M1/50 ,  H03M1/1009 ,  H03M1/1215 ,  H03M1/1245

Abstract: The invention is notably directed to a voltage-to-time converter comprising a first interleaving stage configured to perform a sampling of an input voltage, thereby generating a first set of sampled voltage signals. The first interleaving stage is further configured to perform a first voltage-to-time conversion in an interleaved manner, thereby generating a first set of time-interleaved signals in the time domain. A second interleaving stage is configured to perform a time-to-voltage conversion of the first set of time-interleaved signals, thereby generating a second set of sampled voltage signals. The second interleaving stage is further configured perform a second voltage-to-time conversion in an interleaved manner, thereby generating a second set of time-interleaved signals in the time domain.
The invention further concerns a related design structure and a related method.

公开(公告)号：US20230178642A1

公开(公告)日：2023-06-08

申请号：US17542485

申请日：2021-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cezar Bogdan Zota ,  Thomas Morf ,  Eunjung Cha ,  Peter Mueller

IPC: H01L29/778 ,  H01L29/12 ,  H01L29/66

CPC classification number: H01L29/7783 ,  H01L29/122 ,  H01L29/66462

Abstract: A superconductor transistor structure includes a source electrode and a drain electrode on a same plane as the source electrode. There is a channel region on top of the source and drain electrodes and configured to carry a current. A gate structure comprising a metallic material is on top of the channel region. The source and drain are located on a side that is opposite to that of the gate structure, with respect to the channel region.