公开(公告)号：US11322444B2

公开(公告)日：2022-05-03

申请号：US15934343

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Hiroki Tanaka ,  Robert May ,  Sameer Paital ,  Bai Nie ,  Jesse Jones ,  Chung Kwang Christopher Tan

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

公开(公告)号：US20220122935A1

公开(公告)日：2022-04-21

申请号：US17563995

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Sri Ranga Sai Boyapati ,  Hiroki Tanaka ,  Robert A. May

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498

Abstract: An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.

公开(公告)号：US11309239B2

公开(公告)日：2022-04-19

申请号：US17075533

申请日：2020-10-20

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Jung Kyu Han ,  Ali Lehaf ,  Steve Cho ,  Thomas Heaton ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US11264346B2

公开(公告)日：2022-03-01

申请号：US15857332

申请日：2017-12-28

Applicant: INTEL CORPORATION

Inventor： Kristof Darmawikarta ,  Sri Ranga Sai Boyapati ,  Hiroki Tanaka ,  Robert A. May

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498

Abstract: An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.

公开(公告)号：US10854541B2

公开(公告)日：2020-12-01

申请号：US16554008

申请日：2019-08-28

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Jung Kyu Han ,  Ali Lehaf ,  Steve Cho ,  Thomas Heaton ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati

IPC: H01L27/082 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US10453812B2

公开(公告)日：2019-10-22

申请号：US15855961

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta

IPC: H01L23/00 ,  H01L23/485 ,  H01L21/027

Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.

公开(公告)号：US20190304912A1

公开(公告)日：2019-10-03

申请号：US15937645

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20190304890A1

公开(公告)日：2019-10-03

申请号：US15942864

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Hiroki Tanaka ,  Kristof Kuwawi Darmawikarta ,  Oscar Ojeda ,  Arnab Roy ,  Nicholas Haehn

IPC: H01L23/498 ,  H01L23/14 ,  H01L23/00 ,  H01L21/48 ,  H01L21/027 ,  G03F7/039 ,  G03F7/038 ,  G03F7/20 ,  G03F7/26

Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.

公开(公告)号：US10403564B2

公开(公告)日：2019-09-03

申请号：US15859332

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Hiroki Tanaka ,  Robert A. May ,  Kristof Darmawikarta ,  Changhua Liu ,  Chung Kwang Tan ,  Srinivas Pietambaram ,  Sri Ranga Sai Boyapati

IPC: H01L21/027 ,  H01L21/48 ,  H01L23/485 ,  H01L23/498 ,  H01L23/00

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US20190198467A1

公开(公告)日：2019-06-27

申请号：US15855961

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta

IPC: H01L23/00 ,  H01L23/485 ,  H01L21/027

Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.