公开(公告)号：US10884739B2

公开(公告)日：2021-01-05

申请号：US15989105

申请日：2018-05-24

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/02 ,  G06F12/0862 ,  G06F9/38 ,  G06F12/0875

Abstract: Systems and methods for load canceling in a processor that is connected to an external interconnect fabric are disclosed. As a part of a method for load canceling in a processor that is connected to an external bus, and responsive to a flush request and a corresponding cancellation of pending speculative loads from a load queue, a type of one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor, is converted from load to prefetch. Data corresponding to one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor is accessed and returned to cache as prefetch data. The prefetch data is retired in a cache location of the processor.

公开(公告)号：US10585804B2

公开(公告)日：2020-03-10

申请号：US15806178

申请日：2017-11-07

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/00 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/0804 ,  G06F12/0837 ,  G06F12/0897

Abstract: Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the cache is notified that the cache flush is completed. Subsequent to the notifying, access is provided to data then present in the write-back data holding buffer to determine if data then present in the write-back data holding buffer is flagged.

公开(公告)号：US10073781B2

公开(公告)日：2018-09-11

申请号：US14515345

申请日：2014-10-15

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan

IPC: G06F12/0831 ,  G06F12/0817

CPC classification number: G06F12/0833 ,  G06F12/0824

Abstract: Systems and methods for invalidating a way of a directory for non-home locations (DNHL) set that stores an identifier of a home location of an address is disclosed. As a part of a method, a request to store data in a location of a special cache that is being tracked by the way of the DNHL set is accessed, it is determined if an address stored in the location of the special cache is stored in a non-home location, a DNHL set is identified that tracks the location of the special cache if the address is not stored in a non-home location, and a set and way of the location of the special cache is compared with a set and way identifier stored in each way of the DNHL set. The way of the DNHL set that stores a matching set and way identifier is invalidated.

公开(公告)号：US09965414B2

公开(公告)日：2018-05-08

申请号：US15603407

申请日：2017-05-23

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Aleksey Gorelov

IPC: G06F13/26

CPC classification number: G06F13/26

Abstract: Methods for managing inter-CPU interrupts between sending and receiving CPUs are disclosed. As a part of a method, a target CPU identifier and an interrupt number is written in an interrupt send register of an interrupt sending CPU, the interrupt number is written into one of a plurality of locations of an interrupt receive register corresponding to the target CPU, an identifier of the location of the highest priority interrupt of a plurality of interrupts received by the interrupt receive register is written in an interrupt pick register, the interrupt pick register is read to determine the highest priority interrupt and a matrix associated with the target CPU is read to determine the sender of the highest priority interrupt. The highest priority interrupt is processed.

公开(公告)号：US09767038B2

公开(公告)日：2017-09-19

申请号：US15276664

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/12 ,  G06F12/1027 ,  G06F12/0802 ,  G06F12/1045 ,  G06F12/0875

CPC classification number: G06F12/1027 ,  G06F12/0802 ,  G06F12/0875 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/608 ,  G06F2212/651 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.

公开(公告)号：US20170255576A1

公开(公告)日：2017-09-07

申请号：US15603407

申请日：2017-05-23

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Aleksey Gorelov

IPC: G06F13/26

CPC classification number: G06F13/26

Abstract: Methods for managing inter-CPU interrupts between sending and receiving CPUs are disclosed. As a part of a method, a target CPU identifier and an interrupt number is written in an interrupt send register of an interrupt sending CPU, the interrupt number is written into one of a plurality of locations of an interrupt receive register corresponding to the target CPU, an identifier of the location of the highest priority interrupt of a plurality of interrupts received by the interrupt receive register is written in an interrupt pick register, the interrupt pick register is read to determine the highest priority interrupt and a matrix associated with the target CPU is read to determine the sender of the highest priority interrupt. The highest priority interrupt is processed.

公开(公告)号：US20170228323A1

公开(公告)日：2017-08-10

申请号：US15353053

申请日：2016-11-16

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/128 ,  G06F12/0811 ,  G06F12/0808

CPC classification number: G06F12/128 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/126 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/70

Abstract: Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.

公开(公告)号：US09678903B1

公开(公告)日：2017-06-13

申请号：US14515379

申请日：2014-10-15

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Aleksey Gorelov

IPC: G06F13/26

CPC classification number: G06F13/26

Abstract: Methods for managing inter-CPU interrupts between sending and receiving CPUs are disclosed. As a part of a method, a target CPU identifier and an interrupt number is written in an interrupt send register of an interrupt sending CPU, the interrupt number is written into one of a plurality of locations of an interrupt receive register corresponding to the target CPU, an identifier of the location of the highest priority interrupt of a plurality of interrupts received by the interrupt receive register is written in an interrupt pick register, the interrupt pick register is read to determine the highest priority interrupt and a matrix associated with the target CPU is read to determine the sender of the highest priority interrupt. The highest priority interrupt is processed.