-
公开(公告)号：US10402322B2
公开(公告)日：2019-09-03
申请号：US15686721
申请日：2017-08-25
申请人： Intel Corporation
IPC分类号： G06F12/02 , G06F12/08 , G06F12/10 , G06F9/38 , G06F12/0802 , G06F12/1045
摘要： Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired from the store queue. Loads that are younger than the stores that occupied the store queue before the remapping are prevented from being dispatched and executed until the stores that occupied the store queue before the remapping have left the store queue and become globally visible.
-
公开(公告)号：US09720839B2
公开(公告)日：2017-08-01
申请号：US14922035
申请日：2015-10-23
申请人： Intel Corporation
IPC分类号： G06F12/08 , G06F12/0846 , G06F12/0895
CPC分类号： G06F12/0846 , G06F12/0848 , G06F12/0895 , G06F2212/1021 , G06F2212/6082
摘要： Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data.
-
3.发明授权公开(公告)号：US09720831B2
公开(公告)日：2017-08-01
申请号：US14922042
申请日：2015-10-23
申请人： Intel Corporation
IPC分类号： G06F12/08 , G06F12/0811 , G06F12/0815 , G06F12/0804 , G06F12/0897 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0815 , G06F12/0897 , G06F12/12 , G06F2212/1016 , G06F2212/1032 , G06F2212/1048 , G06F2212/283 , G06F2212/608
摘要： A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.
-
4.发明授权公开(公告)号：US09665468B2
公开(公告)日：2017-05-30
申请号：US13970344
申请日：2013-08-19
申请人： Intel Corporation
CPC分类号： G06F11/26 , G06F11/2236 , G06F11/3648 , G06F11/3656
摘要： Methods for invasive debug of a processor without processor execution of instructions are disclosed. As a part of a method, a memory mapped I/O of the processor is accessed using a debug bus and an operation is initiated that causes a debug port to gain access to registers of the processor using the memory mapped I/O. The invasive debug of the processor is executed from the debug port via registers of the processor.
-
公开(公告)号：US11314647B2
公开(公告)日：2022-04-26
申请号：US16725838
申请日：2019-12-23
申请人： Intel Corporation
IPC分类号： G06F12/0831 , G06F12/1045 , G06F12/0811 , G06F12/0817 , G06F12/0855
摘要： Methods and systems for managing synonyms in VIPT caches are disclosed. A method includes tracking lines of a copied cache using a directory, examining a specified bit of a virtual address that is associated with a load request and determining its status and making an entry in one of a plurality of parts of the directory based on the status of the specified bit of the virtual address that is examined. The method further includes updating one of, and invalidating the other of, a cache line that is associated with the virtual address that is stored in a first index of the copied cache, and a cache line that is associated with a synonym of the virtual address that is stored at a second index of the copied cache, upon receiving a request to update a physical address associated with the virtual address.
-
公开(公告)号：US10552334B2
公开(公告)日：2020-02-04
申请号：US15469457
申请日：2017-03-24
申请人： Intel Corporation
IPC分类号： G06F12/00 , G06F13/00 , G06F12/0897 , G06F12/0855 , G06F9/38 , G06F12/0862 , G06F12/0864 , G06F12/0875
摘要： A method and system acquires cache line data associated with a load from respective hierarchical cache data storage components. As a part of the method and system, a store queue is accessed for one or more portions of a cache line associated with the load, and, if the one or more portions of the cache line is held in the store queue, the one or more portions of the cache line is stored in a load queue location associated with the load. The load is completed if the one or more portions of the cache line stored in the load queue location includes all portions of the cache line associated with the load.
-
7.发明授权公开(公告)号：US10296432B2
公开(公告)日：2019-05-21
申请号：US15586019
申请日：2017-05-03
申请人： Intel Corporation
摘要： Methods for invasive debug of a processor without processor execution of instructions are disclosed. As a part of a method, a memory mapped I/O of the processor is accessed using a debug bus and an operation is initiated that causes a debug port to gain access to registers of the processor using the memory mapped I/O. The invasive debug of the processor is executed from the debug port via registers of the processor.
-
公开(公告)号：US10210101B2
公开(公告)日：2019-02-19
申请号：US15823432
申请日：2017-11-27
申请人： Intel Corporation
IPC分类号： G06F12/126 , G06F12/128 , G06F12/0802 , G06F12/0808 , G06F12/0811
摘要： Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.
-
公开(公告)号：US10073780B2
公开(公告)日：2018-09-11
申请号：US14515333
申请日：2014-10-15
申请人： Intel Corporation
IPC分类号： G06F12/0831 , G06F12/0817
CPC分类号： G06F12/0833 , G06F12/0824
摘要： Systems and methods for tracking addresses stored in non-home locations in a cache. A method includes determining if an address that is to be stored in a cache is to be stored in a non-home location, determining if a directory has a location available for storing an identifier of the non-home location and if one or more locations of the directory are available for storing an identifier of the non-home location, storing an identifier of the non-home location in one of the one or more locations of the directory. The method further includes invalidating a non-home location in the cache that corresponds to one of the one or more locations of the directory, if none of the one or more locations of the directory are available for storing an identifier of the non-home location, and storing an identifier of the non-home location in the one of the one or more locations.
-
10.发明授权公开(公告)号：US10013254B2
公开(公告)日：2018-07-03
申请号：US15244873
申请日：2016-08-23
申请人： Intel Corporation
IPC分类号： G06F12/00 , G06F9/30 , G06F12/02 , G06F12/0862 , G06F9/38 , G06F12/0875
CPC分类号： G06F9/30043 , G06F9/3842 , G06F9/3861 , G06F12/0215 , G06F12/0862 , G06F12/0875 , G06F2212/452
摘要： Systems and methods for load canceling in a processor that is connected to an external interconnect fabric are disclosed. As a part of a method for load canceling in a processor that is connected to an external bus, and responsive to a flush request and a corresponding cancellation of pending speculative loads from a load queue, a type of one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor, is converted from load to prefetch. Data corresponding to one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor is accessed and returned to cache as prefetch data. The prefetch data is retired in a cache location of the processor.
-
-
-
-
-
-
-
-
-
搜索结果
38 条记录 (耗时 0.017 秒)
