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公开(公告)号：US20210409035A1
公开(公告)日：2021-12-30
申请号：US16912733
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Christian Lindholm , Hundo Shin , Martin Clara
Abstract: An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.
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公开(公告)号：US11044137B1
公开(公告)日：2021-06-22
申请号：US16724458
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Kameran Azadet , Martin Clara , Daniel Gruber , Christian Lindholm , Hundo Shin
Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.
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33.发明授权公开(公告)号：US12074606B2
公开(公告)日：2024-08-27
申请号：US17131811
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , Christian Lindholm , Martin Clara , Giacomo Cascio
IPC: H03M1/08 , H03K19/003 , H03K19/0185 , H04B1/12
CPC classification number: H03M1/0827 , H03K19/00384 , H03K19/018578 , H04B1/12
Abstract: A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.
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公开(公告)号：US12063050B2
公开(公告)日：2024-08-13
申请号：US17754309
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Albert Molina , Kameran Azadet , Martin Clara , Matteo Camponeschi , Christian Lindholm
CPC classification number: H03M1/466
Abstract: An analog-to-digital converter comprising a plurality of sampling cells. At least one of the plurality of sampling cells comprises a capacitive element coupled to a cell output of the at least one of the plurality of sampling cells, wherein a cell output signal is provided at the cell output. The at least one of the plurality of sampling cells further comprises a first cell input for receiving an input signal to be digitized, and a second cell input for receiving a calibration signal. Additionally, the at least one of the plurality of sampling cells comprises a first switch circuit capable of selectively coupling the first cell input to the capacitive element based on a clock signal, and a second switch circuit capable of selectively coupling the second cell input to the capacitive element, wherein a size of the second switch circuit is smaller than a size of the first switch circuit.
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公开(公告)号：US12034452B2
公开(公告)日：2024-07-09
申请号：US17132000
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , Michael Kalcher , Martin Clara
Abstract: A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by ri bit positions for the i-th second digital control code, wherein ri is an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.
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Patent Agency Ranking
公开(公告)号：US11489536B1
公开(公告)日：2022-11-01
申请号：US17358093
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Martin Clara , Daniel Gruber , Giacomo Cascio , Albert Molina
Abstract: Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry includes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry configured to generate, based on the calibration signal, a neutralization signal for mitigating an unwanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.
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公开(公告)号：US11277146B2
公开(公告)日：2022-03-15
申请号：US16912733
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Christian Lindholm , Hundo Shin , Martin Clara
Abstract: An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.
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公开(公告)号：US11183993B2
公开(公告)日：2021-11-23
申请号：US16724564
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Hundo Shin , Kameran Azadet , Martin Clara , Daniel Gruber
Abstract: An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.
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公开(公告)号：US11177820B2
公开(公告)日：2021-11-16
申请号：US16933292
申请日：2020-07-20
Applicant: Intel Corporation
Inventor： Albert Molina , Martin Clara , Matteo Camponeschi , Christian Lindholm , Kameran Azadet
Abstract: A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells. The at least one comparator circuit is configured to output a comparison signal based on the cell output signals of the sampling cells. Additionally, the SAR ADC comprises a calibration circuit configured to supply at least one respective control signal to the respective second switch circuit of the sampling cells for controlling the second switch circuits.
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公开(公告)号：US20210194747A1
公开(公告)日：2021-06-24
申请号：US16724458
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Kameran Azadet , Martin Clara , Daniel Gruber , Christian Lindholm , Hundo Shin
Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.
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