公开(公告)号：US10541615B1

公开(公告)日：2020-01-21

申请号：US16021712

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Amit Jain ,  Sameer Shekhar ,  Alexander Lyakhov ,  Jonathan P. Douglas ,  Vivek Saxena

IPC: H02M3/158

Abstract: Techniques and mechanisms for mitigating an overshoot of a supply voltage provided with a voltage regulator (VR). In an embodiment, buck converter functionality of a VR is provided with first circuitry comprising a first inductor and first switch circuits variously coupled thereto. Second circuitry of the VR comprises a second inductor and second switch circuits variously coupled thereto. In response to an indication of a voltage overshoot condition, respective states of the first switch circuits and the second switch circuits are configured to enable a conductive path for dissipating energy with the first inductor, the second inductor, and various ones of the first switch circuits and the second switch circuits. In another embodiment, mitigating the voltage overshoot condition comprises alternately toggling between two different configurations of the second switch circuits.

公开(公告)号：US20190384367A1

公开(公告)日：2019-12-19

申请号：US16551523

申请日：2019-08-26

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Mark Carbone ,  Merwin M. Brown

IPC: G06F1/20 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a plurality of chiplets, a plurality of resources, a system thermal engine, and at least one processor. The at least one processor is configured to cause the system thermal engine to monitor the plurality of chiplets, where the plurality of chiplets are part of a multi-chip module, determine that a first chiplet from the plurality of chiplets has reached a threshold temperature, and reduce power to the first chiplet without reducing power to the other chiplets in the plurality of chiplets.

公开(公告)号：US20180286556A1

公开(公告)日：2018-10-04

申请号：US15477080

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Amit K. Jain ,  Sameer Shekhar ,  John T. Vu

IPC: H01F27/02 ,  H01F41/04 ,  H01F27/29 ,  H01F27/06

Abstract: An inductor of an integrated circuit can include one or more magnetically transparent and non-conductive layers, a plurality of conductive elements, and a plurality of through hole conductor elements. The plurality of conductive elements can be disposed about opposite sides of each of the one or more non-conductive layers. The plurality of through hole conductive elements can be disposed through the one or more non-conductive layers and electrically coupling selected ones of the plurality of conductive elements in one or more conductive paths configured such that a magnetic field generated in response to a current flow in the one or more conductive paths opposes changes in the current flow.