公开(公告)号：US07712010B2

公开(公告)日：2010-05-04

申请号：US11424285

申请日：2006-06-15

申请人： Timothy J. Dell

发明人： Timothy J. Dell

IPC分类号： H03M13/00

CPC分类号： G06F11/10 ,  H04L1/0045

摘要： Systems, method, and computer program products for utilizing a spare lane for additional checkbits. Systems include computer, storage or communications systems with bitlanes for transferring error correcting code (ECC) words in packets over a bus in multiple cycles, a spare bitlane available to the bus, a spared mode and an initial mode. The spared mode is executed when the spare bitlane has been deployed as a replacement bitlane for carrying data for one of the other bitlanes. The initial mode is executed when the spare bitlane has not been deployed as a replacement bitlane. The initial mode includes utilizing the spare bitlane for carrying one or more additional ECC checkbits. The initial mode provides at least one of a more robust error detecting function for the bus than the spared mode and a more robust error correcting function for the bus than the spared mode.

摘要翻译： 系统，方法和计算机程序产品，用于利用备用通道进行其他校验。 系统包括具有位线的计算机，存储或通信系统，用于在多个周期中通过总线传送分组中的纠错码（ECC）字，可用于总线的备用位元，冗余模式和初始模式。 当备用位元件被部署为用于承载其他位位之一的数据的替换位元时，执行备用模式。 当备用位元未被部署为替换位元时，执行初始模式。 初始模式包括利用备用位元来承载一个或多个附加的ECC校验位。 初始模式提供总线比冗余模式更鲁棒的错误检测功能中的至少一个，并且比冗余模式提供总线的更稳健的误差校正功能中的至少一个。

公开(公告)号：US06467018B1

公开(公告)日：2002-10-15

申请号：US09225536

申请日：1999-01-04

申请人： Timothy J. Dell ,  Mark W. Kellogg

发明人： Timothy J. Dell ,  Mark W. Kellogg

IPC分类号： G06F1200

CPC分类号： G06F13/1647

摘要： An improved memory card and its use in a computer system is provided. The computer system has a system bus which provides requests from a CPU to a memory controller, which then provides signals to the memory card or module or a memory bus. The memory card is provided with first and second banks of DRAMs, a memory card bus and a DSP. Logic circuitry including a memory card data bus controller provides communication of the DSP with the banks of DRAM chips. Logic circuitry is also provided which can selectively connect the DSP to either the first or second bank of DRAMs and selectively connect the memory bus with the other bank of DRAMs or with both banks of DRAMs. Hence when the CPU is accessing one bank of DRAMS the DSP can access the other bank of DRAMs thus allowing the DSP to function utilizing the bank of DRAMs not being accessed by the memory bus to service the CPU or some I/O device.

摘要翻译： 提供了一种改进的存储卡及其在计算机系统中的应用。 计算机系统具有系统总线，其提供从CPU到存储器控制器的请求，然后存储器控制器向存储卡或模块或存储器总线提供信号。 存储卡设置有第一和第二组DRAM，存储卡总线和DSP。 包括存储卡数据总线控制器的逻辑电路提供DSP与DRAM芯片组的通信。 还提供了逻辑电路，其可以选择性地将DSP连接到第一或第二组DRAM并且选择性地将存储器总线与另一组DRAM或两组DRAM连接。 因此，当CPU正在访问一组DRAMS时，DSP可以访问另一组DRAM，从而允许DSP利用由存储器总线访问的DRAM组来对CPU或一些I / O设备进行服务。

公开(公告)号：US06349390B1

公开(公告)日：2002-02-19

申请号：US09224990

申请日：1999-01-04

申请人： Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg

发明人： Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg

IPC分类号： G06F1110

CPC分类号： G06F11/106

摘要： A memory module for attachment to a computer system having a memory bus and a method of using the memory module for error correction by scrubbing soft errors on-board the module is provided. The module includes a printed circuit card with memory storage chips on the card to store data bits and associated ECC check bits. Tabs are provided on the circuit card to couple the card to the memory bus of the computer system. Logic circuitry selectively operatively connects and disconnects the memory chip and the memory bus. A signal processor is connected in circuit relationship with the memory chips. The logic circuitry selectively permits the signal processor to read the stored data bits and associated check bits from the memory chips, recalculate the check bits from the read stored data bits, compare the recalculated check bits with the stored check bits, correct all at least one bit errors in the store data bits and stored associated check bits and re-store the correct data bits and associated check bits in the memory chips. When the memory chips and the memory bus are disconnected, single bit soft errors occurring during storage of the data bits and check bits are corrected periodically before the data is read from the memory chips to the data bus on a read operation.

摘要翻译： 提供了一种用于附接到具有存储器总线的计算机系统的存储器模块，以及通过擦除模块上的软错误来使用存储器模块进行纠错的方法。 该模块包括在卡上具有存储器存储芯片的印刷电路卡，以存储数据位和相关联的ECC校验位。 在电路卡上提供标签以将该卡耦合到计算机系统的存储器总线。 逻辑电路选择性地操作地连接和断开存储器芯片和存储器总线。 信号处理器与存储器芯片以电路关系连接。 逻辑电路选择性地允许信号处理器从存储器芯片读取存储的数据位和相关的校验位，从读取的存储的数据位重新计算校验位，将重新计算的校验位与存储的校验位进行比较，校正所有至少一个 存储数据位和存储的相关检查位中的位错误并且将存储器芯片中的正确数据位和相关联的校验位重新存储。 当存储器芯片和存储器总线断开时，在存储数据位和校验位期间发生的单位软错误在数据从读存储器芯片读取到数据总线之前被周期性地校正。

公开(公告)号：US06347367B1

公开(公告)日：2002-02-12

申请号：US09240647

申请日：1999-01-29

申请人： Timothy J. Dell ,  Steven A. Grundon ,  Mark W. Kellogg

发明人： Timothy J. Dell ,  Steven A. Grundon ,  Mark W. Kellogg

IPC分类号： G06F1200

CPC分类号： G06F13/4239

摘要： The disclosed invention relates generally to electronic data storage systems that access data storage memory modules via a data bus comprised of multiple data query lines and, more particularly, to an electronic data storage system provided with a data bus that can be selectively provided with terminations thereby permitting the data storage memory to use either modules that require that the data query lines be open-ended, i.e., without terminations or modules that require that the data bus be terminated and to a method for operating such a system. The present invention is particularly directed to a single memory system that can accommodate either 3.3V DIMMs or DDR DIMMs. This is especially accomplished by providing the processor circuit, used in memory storage systems, with both (3.3V) receiver/driver circuits and double rate (DDR) receiver/driver circuits, with an identification circuit for identifying the type of DIMMs in the memory system coupled thereto, a selection circuit for selecting the receiver/driver circuits required to access the identified DIMMs, and switch for adding or removing terminations to the data query lines, interconnecting the selected receiver driver circuits to identified DIMMS. Thus the invention provides a memory system that can access either 3.3V DIMMs or DDR DIMMs and automatically provide the proper terminations on the data bus used to access the DIMMs.

摘要翻译： 所公开的发明一般涉及经由包括多条数据查询线的数据总线访问数据存储存储器模块的电子数据存储系统，更具体地说，涉及一种具有数据总线的电子数据存储系统，该数据总线可选择性地提供终端 允许数据存储存储器使用要求数据查询行是开放式的模块，即，不需要终止数据总线的终端或模块以及用于操作这样的系统的方法。 本发明特别涉及可容纳3.3V DIMM或DDR DIMM的单个存储器系统。 这通过在存储器存储系统中使用处理器电路（3.3V）接收器/驱动器电路和双速率（DDR）接收器/驱动器电路）来实现，其中识别电路用于识别存储器中的DIMM的类型 耦合到其上的系统，用于选择访问所识别的DIMM所需的接收机/驱动器电路的选择电路，以及用于向数据查询线路添加或移除终端的切换，将所选择的接收机驱动器电路互连到所识别的DIMMS。 因此，本发明提供了一种存储系统，其可以访问3.3V DIMM或DDR DIMM，并且在用于访问DIMM的数据总线上自动提供适当的终端。

公开(公告)号：US06233639B1

公开(公告)日：2001-05-15

申请号：US09225524

申请日：1999-01-04

申请人： Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  Clarence R. Ogilvie ,  Paul C. Stabler

发明人： Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  Clarence R. Ogilvie ,  Paul C. Stabler

IPC分类号： G06F1300

CPC分类号： G11C5/066

摘要： A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data. This serial information is received by the system memory controller which packets it, and, upon completion, outputs the information rapidly on a parallel bus, e.g. a PCI bus to the device which needs the information.

摘要翻译： 在具有DSP和存储器总线控制器的存储卡上提供串行总线和通过系统存储器控制器与计算机系统上的设备的连接，以允许存储卡上的DSP访问系统设备而不使用系统 内存总线 串行总线是通过系统存储器控制器将设备连接到DSP的双线串行总线。 如果多个存储卡存在于DSP或多于一个设备正在争取访问，则系统存储器控制器或仲裁每个存储卡或竞争设备的访问。 在这种情况下，当串行总线想要访问特定设备时，串行总线将向系统存储器控制器发信号通知，并且系统存储器控制器将充当仲裁器以授予或不授予对请求访问的特定存储卡或设备的访问权限。 如果访问被授予，总线存储器控制器在串行总线上输出所需的控制或命令字，然后输出地址和所需的数据。 该串行信息由系统存储器控制器接收，该系统存储器控制器对其进行分组，并且在完成时，在并行总线上快速地输出信息，例如， PCI总线到需要信息的设备。

公开(公告)号：US06178517B1

公开(公告)日：2001-01-23

申请号：US09121933

申请日：1998-07-24

申请人： Claude L. Bertin ,  Timothy J. Dell ,  Erik L. Hedberg ,  Mark W. Kellogg

发明人： Claude L. Bertin ,  Timothy J. Dell ,  Erik L. Hedberg ,  Mark W. Kellogg

IPC分类号： G06F1200

CPC分类号： G06F13/1684 ,  Y02D10/14

摘要： A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.

摘要翻译： 高带宽DRAM具有将DRAM连接到处理器的两个单独的总线网络。 一个总线网络是高速（例如，500MHz）8：1或16：1多路复用I / O总线，第二个是较慢（例如，64位）总线。 例如，高速总线用于需要快速访问DRAM存储器阵列中大量位的图形密集型应用。 这当然会导致更高的功率需求。 由于并非所有应用都需要在DRAM和处理器之间传输大量数据，所以为这些不太要求苛刻的应用程序提供较慢的总线，例如文字处理器，电子表格等。 较慢的总线需要更少的功率来进行操作，因此导致省电模式，其中尤其有助于延长电池寿命。

公开(公告)号：US5896404A

公开(公告)日：1999-04-20

申请号：US833371

申请日：1997-04-04

申请人： Mark W. Kellogg ,  Timothy J. Dell ,  Erik L. Hedberg ,  Claude L. Bertin

发明人： Mark W. Kellogg ,  Timothy J. Dell ,  Erik L. Hedberg ,  Claude L. Bertin

IPC分类号： G06F12/16 ,  G06F11/10 ,  G11C7/10 ,  G11C11/401 ,  G11C29/42 ,  G11C29/00

CPC分类号： G06F11/1008 ,  G11C7/1018 ,  G06F11/1052

摘要： A Dynamic Random Access Memory (DRAM) with a burst length programmable as eight (8) or nine (9) bytes. The DRAM array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is programmed in Normal mode, the burst length is 8 and the entire array address space is available for data storage. When the DRAM is programmed for error checking (ECC mode), the burst length is nine and the array is reconfigured with part of the array providing the ninth byte. The DRAM's address space is reduced by one-eighth in ECC mode. Preferably, all nine locations are in the same page, with each page being divided into eight equal portions. In Normal mode all eight equal portions are data storage; and, in ECC mode, seven-eighths of the page is data storage, the remaining one eighth being assigned to check bit storage.

摘要翻译： 具有可编程为八（8）或九（9）字节的突发长度的动态随机存取存储器（DRAM）。 DRAM阵列分为两个或更多个子阵列，子阵列单元以可寻址的行和列排列。 当DRAM在正常模式下编程时，突发长度为8，整个阵列地址空间可用于数据存储。 当DRAM被编程用于错误检查（ECC模式）时，突发长度为9，并且阵列被配置为提供第九个字节的阵列的一部分。 在ECC模式下，DRAM的地址空间减少了八分之一。 优选地，所有九个位置在同一页面中，每个页面被分成八个相等的部分。 在正常模式下，所有八个相等的部分都是数据存储; 并且在ECC模式中，页面的七分之一是数据存储，剩下的八分之一被分配给校验位存储。

公开(公告)号：US09442816B2

公开(公告)日：2016-09-13

申请号：US13307149

申请日：2011-11-30

申请人： Edgar R. Cordero ,  Timothy J. Dell ,  Joab D. Henderson ,  Anil B. Lingambudi ,  Girisankar Paulraj ,  Diyanesh B. Vidyapoornachary

发明人： Edgar R. Cordero ,  Timothy J. Dell ,  Joab D. Henderson ,  Anil B. Lingambudi ,  Girisankar Paulraj ,  Diyanesh B. Vidyapoornachary

IPC分类号： G06F13/00 ,  G06F11/30 ,  G06F11/16

CPC分类号： G06F11/3037 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/3058 ,  G06F2201/81

摘要： A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory.

摘要翻译： 一种方法，系统和计算机程序产品实现了对系统热条件的计算机系统的存储器性能管理和增强的存储器可靠性。 当主存储器温度达到初始温度阈值时，读取将暂停到主存储器，并将读取提供给镜像存储器对中的镜像存储器，并将写入提供给主存储器和镜像存储器。 如果主存储器温度达到第二温度阈值，则对主存储器的写操作也被停止，并且主存储器通过诸如自定时刷新（STR）的DRAM省电模式被关闭，并且读取和写入被限制为 在镜像存储器对中镜像存储器。 当初级存储器温度降低到低于初始温度阈值时，通过将相干拷贝从镜像存储器写入主存储器来恢复一致性。

公开(公告)号：US08359521B2

公开(公告)日：2013-01-22

申请号：US12018030

申请日：2008-01-22

申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G06F11/1004

摘要： A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line.

摘要翻译： 一种用于提供具有共享错误反馈引脚的存储器件的系统和方法。 该系统包括具有被配置为接收数据比特和CRC比特，CRC接收电路，CRC创建电路，存储器装置垫和驱动器电路的数据接口的存储器装置。 CRC接收电路利用CRC方程来检测一个或多个接收数据和接收的CRC比特中的错误。 CRC创建电路利用CRC方程来创建与要发送到单独设备位的数据一致的CRC位。 存储器件焊盘被配置为报告在接收的数据和接收的CRC位中检测到的任何错误。 驱动器电路连接到存储器件焊盘并与驻留在一个或多个其它存储器件上的一个或多个其它驱动器电路合并到错误报告行中。

公开(公告)号：US20090187794A1

公开(公告)日：2009-07-23

申请号：US12018030

申请日：2008-01-22

申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

IPC分类号： G06F11/00

CPC分类号： G06F11/1004

摘要： A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line.

摘要翻译： 一种用于提供具有共享错误反馈引脚的存储器件的系统和方法。 该系统包括具有被配置为接收数据比特和CRC比特，CRC接收电路，CRC创建电路，存储器装置垫和驱动器电路的数据接口的存储器装置。 CRC接收电路利用CRC方程来检测一个或多个接收数据和接收的CRC比特中的错误。 CRC创建电路利用CRC方程来创建与要发送到单独设备位的数据一致的CRC位。 存储器件焊盘被配置为报告在接收的数据和接收的CRC位中检测到的任何错误。 驱动器电路连接到存储器件焊盘并与驻留在一个或多个其它存储器件上的一个或多个其它驱动器电路合并到错误报告行中。